[Mlir-commits] [mlir] [mlir][ROCDL] Add tensor load and store instructions to ROCDL (PR #165016)

[Alan Li]

================
@@ -663,6 +663,82 @@ def ROCDL_GlobalLoadLDSOp :
   }];
 }
 
+//===---------------------------------------------------------------------===//
+// Tensor load/store intrinsics (available in GFX1250)
+//===---------------------------------------------------------------------===//
+
+def ROCDL_TensorLoadToLDSIntrOp :
+  ROCDL_IntrOp<"tensor.load.to.lds", [], [], [], 0, 0, 1, 0, [4], ["cachePolicy"]> {
+  dag args = (ins Arg<LLVM_VectorOf<I32>, "", [MemRead]>:$dgroup0,
----------------
lialan wrote:

I am not sure if we want `MemRead` here, same as `MemWrite` below.
Here is what I can find:
* the source and dest addresses are encoded in d#group 0 (as per manual), group 1,2,3 are other encodings irrelevant of memory addresses.
* underlying intrinsic has `IntrInaccessibleMemOrArgMemOnly`

I think memory properties are best associated with the ROCDL intrinsic instead of the individual  arguments. @justinrosner 

https://github.com/llvm/llvm-project/pull/165016