[Mlir-commits] [mlir] [MLIR][Conversion] XeGPU to XeVM: create_nd_tdesc - Add support for base memory rank > 2 (PR #164701)

[Sang Ik Lee]

silee2 wrote:

> can you clarify how it is handled when tensor_desc is a block arg or a func arg?

Short answer is, lowering pattern will not handle those cases.
I think func arg case will not happen in practice.
The ops are used as part of device kernel and tensor_desc is not used as a device kernel arg.
Only other case is using tensor_desc as a func arg inside device kernel, but xegpu currently does not support those cases.

Block arg case can be an issue. Block args are used for loops or control flow.
Loop issue can be solved by forcing create_nd_desc to be placed in the current block, but handling control flow cannot be done with a simple restriction.

Will update the PR to search for create_nd_tdesc through block args but not interprocedurally.



https://github.com/llvm/llvm-project/pull/164701