[Mlir-commits] [mlir] [MLIR][XeGPU] Introduce `xegpu::uArch` usage in target-sensitive passes (PR #163801)

[Artem Kroviakov]

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@@ -42,12 +40,61 @@ struct Xe2Plus : public uArch {
               &instrs = {})
       : uArch(archName, archDescription, regInfo, cacheInfo, instrs),
         xeCore(xeCore) {}
+  int getSubgroupSize() const override { return 16; }
+  unsigned getPackedFormatBitSizeGatherScatter() const override { return 32; }
+  unsigned getPackedFormatBitSize() const override { return 16; }
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akroviakov wrote:

For a generic lane data calculation for dpas operands, wouldn't the following format be desired in the dpas propagation
`packingFactor = dpasInst->getOperand*A/B/C*PackingBitSize() / dataElemBitwidth`?

It is not so much about whether we actually consider "packing" C.

https://github.com/llvm/llvm-project/pull/163801