[Mlir-commits] [mlir] [mlir][amdgpu] Add scaled_ext_packed{8, 16} operations (PR #159830)

[Jakub Kuderski]

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@@ -112,6 +112,73 @@ def AMDGPU_ExtPackedFp8Op :
   }];
 }
 
+def IsValidBlockSize: AttrConstraint<
+    CPred<"::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 16 || ::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 32">,
+    "whose value is 16 or 32">;
+
+
+def Vector4Scales :
+  AllOfType<[FixedVectorOfLengthAndType<[4], [F8E8M0FNU]>],
+    "vector of 4 F8E8M0FNU scales",
+    "::mlir::VectorType">,
+  BuildableType<"::mlir::VectorType::get({4}, $_builder.getType<::mlir::Float8E8M0FNUType>());">;
----------------
kuhar wrote:

My issue is not with the exact mechanism of how the type is enforced/verified, it's more that have a strong preference for all non-trivial types to appear in the assembly format. Here the operation omits an argument type, but it could also be that the producer of the argument omits the return type in its assembly format, making it close to impossible to tell what an SSA value is

https://github.com/llvm/llvm-project/pull/159830