[Mlir-commits] [mlir] [mlir][amdgpu] Add scaled_ext_packed{8, 16} operations (PR #159830)

Krzysztof Drewniak llvmlistbot at llvm.org
Thu Oct 16 15:34:45 PDT 2025


================
@@ -112,6 +112,73 @@ def AMDGPU_ExtPackedFp8Op :
   }];
 }
 
+def IsValidBlockSize: AttrConstraint<
+    CPred<"::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 16 || ::llvm::cast<::mlir::IntegerAttr>($_self).getInt() == 32">,
+    "whose value is 16 or 32">;
+
+
+def Vector4Scales :
+  AllOfType<[FixedVectorOfLengthAndType<[4], [F8E8M0FNU]>],
----------------
krzysz00 wrote:

This technically allows `vector<2x2xf8E8M0FNU>`

https://github.com/llvm/llvm-project/pull/159830


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