[Mlir-commits] [mlir] d45b427 - [MLIR] Define memory effects for `memref.prefetch` operation (#151261)

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Author: Alexandre Eichenberger
Date: 2025-10-08T08:36:57+01:00
New Revision: d45b427ed476529a6cc52566c03839ad976ac37f

URL: https://github.com/llvm/llvm-project/commit/d45b427ed476529a6cc52566c03839ad976ac37f
DIFF: https://github.com/llvm/llvm-project/commit/d45b427ed476529a6cc52566c03839ad976ac37f.diff

LOG: [MLIR] Define memory effects for `memref.prefetch` operation (#151261)

Currently `memref.prefetch` has no memory side effects, which are
necessary for some optimizations.

This PR adds the needed side effect, as recommended in
https://discourse.llvm.org/t/modeling-volatility-with-memory-effects/67946

This PR was created after a discussion on this specific topic here
https://discourse.llvm.org/t/memref-prefetch-op-has-no-memory-side-effects-decoration-in-the-def-td-file/87482

---------

Signed-off-by: Alexandre Eichenberger <alexe at us.ibm.com>

Added: 
    

Modified: 
    mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
    mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir

Removed: 
    


################################################################################
diff  --git a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
index d4d67bfb278d5..40b7d7e33d5c2 100644
--- a/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
+++ b/mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
@@ -1414,7 +1414,14 @@ def MemRef_PrefetchOp : MemRef_Op<"prefetch"> {
     instruction cache.
   }];
 
-  let arguments = (ins AnyMemRef:$memref, Variadic<Index>:$indices,
+  // The memref argument is labeled with a side effect to enforce a
+  // relative ordering of the prefetch and other memory operations targeting
+  // that memory stream.
+  // We need it to be a write otherwise the operation would be trivially removed
+  // since it does not produce a value.
+
+  let arguments = (ins Arg<AnyMemRef, "prefetch address", [MemWrite]> :$memref,
+                       Variadic<Index>:$indices,
                        BoolAttr:$isWrite,
                        ConfinedAttr<I32Attr, [IntMinValue<0>,
                                           IntMaxValue<3>]>:$localityHint,

diff  --git a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
index c50c25ad8194f..fc137f1f2f722 100644
--- a/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
+++ b/mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/misc-other.mlir
@@ -17,4 +17,12 @@ func.func @func_with_assert(%arg0: index, %arg1: index) {
 func.func @func_with_assume_alignment(%arg0: memref<128xi8>) {
   %0 = memref.assume_alignment %arg0, 64 : memref<128xi8>
   return
-}
\ No newline at end of file
+}
+
+// CHECK-LABEL: func @func_with_prefetch(
+//       CHECK: memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32>
+func.func @func_with_prefetch(%arg0: memref<4x8xf32>) {
+  %c0 = arith.constant 0 : index
+  memref.prefetch %arg0[%c0, %c0], read, locality<1>, data : memref<4x8xf32>
+  return
+}