[Mlir-commits] [mlir] [MLIR][XeVM] Add XeVM 1D block operations to OpenCL calls conversion. (PR #161702)
Nishant Patel
llvmlistbot at llvm.org
Mon Oct 6 15:15:29 PDT 2025
================
@@ -620,6 +629,77 @@ class LoadStorePrefetchToOCLPattern : public OpConversionPattern<OpType> {
return success();
}
};
+
+template <typename OpType>
+class BlockLoadStore1DToOCLPattern : public OpConversionPattern<OpType> {
+ using OpConversionPattern<OpType>::OpConversionPattern;
+ LogicalResult
+ matchAndRewrite(OpType op, typename OpType::Adaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ constexpr bool isStore = std::is_same_v<OpType, xevm::BlockStoreOp>;
+ // Get OpenCL function name
+ // https://registry.khronos.org/OpenCL/extensions/
+ // intel/cl_intel_subgroup_local_block_io.html
+ std::string funcName{"intel_sub_group_block_"};
+ funcName += isStore ? "write_u" : "read_u";
+ VectorType vecType;
+ if constexpr (isStore)
+ vecType = op.getVal().getType();
+ else
+ vecType = op.getType();
+ Type elemType = vecType.getElementType();
+ funcName += getTypeMangling(elemType);
+ if (vecType.getNumElements() > 1)
+ funcName += std::to_string(vecType.getNumElements());
+ SmallVector<Type, 2> argTypes{};
+ // XeVM BlockLoad/StoreOp always use signless integer types
+ // but OpenCL builtins expect unsigned types
+ // use unsigned types for mangling
+ SmallVector<bool, 2> isUnsigned{};
+ // arg0: pointer to the src/dst address
+ // arg1 - only if store : vector to store
+ // Prepare arguments
+ SmallVector<Value, 2> args{};
+ args.push_back(op.getPtr());
+ argTypes.push_back(op.getPtr().getType());
+ isUnsigned.push_back(true);
+ Type retType;
+ if constexpr (isStore) {
+ args.push_back(op.getVal());
+ argTypes.push_back(op.getVal().getType());
+ isUnsigned.push_back(true);
+ retType = LLVM::LLVMVoidType::get(rewriter.getContext());
+ } else {
+ /*
----------------
nbpatel wrote:
commented code
https://github.com/llvm/llvm-project/pull/161702
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