[Mlir-commits] [mlir] [MLIR][NVVM] Add missing rounding modes in fp16x2 conversions (PR #169005)

[LLVM Continuous Integration]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ppc64le-flang-rhel-clang` running on `ppc64le-flang-rhel-test` while building `mlir` at step 6 "test-build-unified-tree-check-flang".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/157/builds/42571

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (test-build-unified-tree-check-flang) failure: 1200 seconds without output running [b'ninja', b'check-flang'], attempting to kill
...
PASS: Flang :: Transforms/debug-omp-target-op-1.fir (4018 of 4029)
PASS: Flang :: Driver/nostdlib.f90 (4019 of 4029)
PASS: Flang :: Transforms/OpenACC/acc-implicit-data-fortran.F90 (4020 of 4029)
PASS: Flang :: Driver/fveclib.f90 (4021 of 4029)
PASS: Flang :: Driver/options-loongarch.f90 (4022 of 4029)
PASS: Flang :: Driver/linker-options.f90 (4023 of 4029)
PASS: Flang :: Driver/fopenmp.f90 (4024 of 4029)
PASS: Flang :: Lower/OpenMP/rtl-flags.f90 (4025 of 4029)
PASS: Flang :: Driver/use-module.f90 (4026 of 4029)
PASS: Flang :: Driver/omp-driver-offload.f90 (4027 of 4029)
command timed out: 1200 seconds without output running [b'ninja', b'check-flang'], attempting to kill
process killed by signal 9
program finished with exit code -1
elapsedTime=3164.749510

```

</details>

https://github.com/llvm/llvm-project/pull/169005