[Mlir-commits] [mlir] [MLIR][LLVM] Support named barrier as a global variable type in llvm dialect (PR #169194)

[llvmlistbot at llvm.org]

https://github.com/PMylon updated https://github.com/llvm/llvm-project/pull/169194

>From f481b21e92406e28ca3be4eceb762fab3644792a Mon Sep 17 00:00:00 2001
From: PMylon <pmylon20 at gmail.com>
Date: Sat, 22 Nov 2025 23:50:39 +0000
Subject: [PATCH] Add support for named barrier as a global variable type in
 MLIR's llvm dialect

---
 mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp     | 4 ++++
 mlir/test/Target/LLVMIR/target-ext-type.mlir | 6 ++++++
 2 files changed, 10 insertions(+)

diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
index ce93d18f56d39..5dc4fa2b2d82f 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
@@ -667,6 +667,7 @@ LogicalResult LLVMStructType::verifyEntries(DataLayoutEntryListRef entries,
 
 static constexpr llvm::StringRef kSpirvPrefix = "spirv.";
 static constexpr llvm::StringRef kArmSVCount = "aarch64.svcount";
+static constexpr llvm::StringRef kAMDGCNNamedBarrier = "amdgcn.named.barrier";
 
 bool LLVM::LLVMTargetExtType::hasProperty(Property prop) const {
   // See llvm/lib/IR/Type.cpp for reference.
@@ -676,6 +677,9 @@ bool LLVM::LLVMTargetExtType::hasProperty(Property prop) const {
     properties |=
         (LLVMTargetExtType::HasZeroInit | LLVM::LLVMTargetExtType::CanBeGlobal);
 
+  if (getExtTypeName() == kAMDGCNNamedBarrier)
+    properties |= LLVMTargetExtType::CanBeGlobal;
+
   return (properties & prop) == prop;
 }
 
diff --git a/mlir/test/Target/LLVMIR/target-ext-type.mlir b/mlir/test/Target/LLVMIR/target-ext-type.mlir
index 6b2d2ea3d4c23..cee630163ca21 100644
--- a/mlir/test/Target/LLVMIR/target-ext-type.mlir
+++ b/mlir/test/Target/LLVMIR/target-ext-type.mlir
@@ -6,6 +6,12 @@ llvm.mlir.global external @global() {addr_space = 0 : i32} : !llvm.target<"spirv
   llvm.return %0 : !llvm.target<"spirv.DeviceEvent">
 }
 
+// CHECK: @amdgcn_named_barrier = internal addrspace(3) global target("amdgcn.named.barrier", 0) poison
+llvm.mlir.global internal @amdgcn_named_barrier() {addr_space = 3 : i32} : !llvm.target<"amdgcn.named.barrier", 0> {
+  %0 = llvm.mlir.poison : !llvm.target<"amdgcn.named.barrier", 0>
+  llvm.return %0 : !llvm.target<"amdgcn.named.barrier", 0>
+}
+
 // CHECK-LABEL: define target("spirv.Event") @func2() {
 // CHECK-NEXT:    %1 = alloca target("spirv.Event"), align 8
 // CHECK-NEXT:    %2 = load target("spirv.Event"), ptr %1, align 8