[Mlir-commits] [mlir] [ROCDL] Added missing `cluster.load.async.to.lds` op (gfx1250) (PR #169042)
Ravil Dorozhinskii
llvmlistbot at llvm.org
Fri Nov 21 06:07:36 PST 2025
https://github.com/ravil-mobile created https://github.com/llvm/llvm-project/pull/169042
* Added missing cluster.load ops with different sizes. Extended all rocdl tests
>From d3e3a5c34c03699a523632b68eb5ffc180e54ced Mon Sep 17 00:00:00 2001
From: ravil-mobile <ravil.aviva.com at gmail.com>
Date: Fri, 21 Nov 2025 14:04:48 +0000
Subject: [PATCH] [ROCDL] Added missing `cluster.load.async.to.lds` op
(gfx1250)
* Added missing cluster.load ops with different sizes. Extended all rocdl tests
---
mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td | 30 +++++++++++++++++++-
mlir/test/Dialect/LLVMIR/rocdl.mlir | 22 +++++++++++---
mlir/test/Target/LLVMIR/rocdl.mlir | 13 +++++++++
3 files changed, 60 insertions(+), 5 deletions(-)
diff --git a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
index 19741f10ce8cc..a6a5422b7f49f 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
@@ -868,7 +868,7 @@ foreach bitsVal = [8, 32, 64, 128] in {
let arguments = !con(args, baseArgs);
let assemblyFormat = [{
$globalPtr `,` $ldsPtr `,` $offset `,` $aux
- attr-dict `:` type($globalPtr) `,` type($ldsPtr)
+ attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
}];
let description = [{
Asynchronously loads }] # !cast<string>(bitsVal) # [{ bits of data from a global memory pointer
@@ -885,6 +885,34 @@ foreach bitsVal = [8, 32, 64, 128] in {
}
}
+foreach bitsVal = [8, 32, 64, 128] in {
+ defvar bitsStr = "b" # !cast<string>(bitsVal);
+ def ROCDL_ClusterLoadAsyncToLDS # !toupper(bitsStr) # Op :
+ ROCDL_IntrOp<"cluster.load.async.to.lds." # bitsStr, [], [], [], 0, 0, 1, 0, [2, 3, 4], ["offset", "cpol", "mask"]> {
+ dag args = (ins Arg<ROCDLGlobalBuffer, "", [MemRead]>:$globalPtr,
+ Arg<ROCDLBufferLDS, "", [MemWrite]>:$ldsPtr,
+ I32Attr:$offset,
+ I32Attr:$cpol,
+ I32Attr:$mask);
+ let arguments = !con(args, baseArgs);
+ let assemblyFormat = [{
+ $globalPtr `,` $ldsPtr `,` $offset `,` $cpol `,` $mask
+ attr-dict `:` qualified(type($globalPtr)) `,` qualified(type($ldsPtr))
+ }];
+ let description = [{
+ Broadcasts memory load of }] # !cast<string>(bitsVal) # [{ bits of data for a cluster of workgroups.
+
+ Available on gfx1250+.
+ }];
+
+ let extraClassDefinition = [{
+ ::llvm::SmallVector<::mlir::Value> $cppClass::getAccessedOperands() {
+ return {getGlobalPtr(), getLdsPtr()};
+ }
+ }];
+ }
+}
+
//===---------------------------------------------------------------------===//
// Tensor load/store intrinsics (available in GFX1250)
//===---------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/LLVMIR/rocdl.mlir b/mlir/test/Dialect/LLVMIR/rocdl.mlir
index 675975ae597ac..38ef97edb1231 100644
--- a/mlir/test/Dialect/LLVMIR/rocdl.mlir
+++ b/mlir/test/Dialect/LLVMIR/rocdl.mlir
@@ -709,13 +709,27 @@ llvm.func @rocdl.global.load.async.to.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3
// CHECK: rocdl.global.load.async.to.lds.b32 %{{.*}}, %{{.*}}, 0, 0
// CHECK: rocdl.global.load.async.to.lds.b64 %{{.*}}, %{{.*}}, 0, 0
// CHECK: rocdl.global.load.async.to.lds.b128 %{{.*}}, %{{.*}}, 0, 0
- rocdl.global.load.async.to.lds.b8 %src, %dst, 0, 0 : <1>, <3>
- rocdl.global.load.async.to.lds.b32 %src, %dst, 0, 0 : <1>, <3>
- rocdl.global.load.async.to.lds.b64 %src, %dst, 0, 0 : <1>, <3>
- rocdl.global.load.async.to.lds.b128 %src, %dst, 0, 0 : <1>, <3>
+ rocdl.global.load.async.to.lds.b8 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.global.load.async.to.lds.b32 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.global.load.async.to.lds.b64 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.global.load.async.to.lds.b128 %src, %dst, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
llvm.return
}
+llvm.func @rocdl.cluster.load.async.to.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
+ // CHECK-LABEL @rocdl.cluster.load.async.to.lds
+ // CHECK: rocdl.cluster.load.async.to.lds.b8 %{{.*}}, %{{.*}}, 0, 0, 0
+ // CHECK: rocdl.cluster.load.async.to.lds.b32 %{{.*}}, %{{.*}}, 0, 0, 0
+ // CHECK: rocdl.cluster.load.async.to.lds.b64 %{{.*}}, %{{.*}}, 0, 0, 0
+ // CHECK: rocdl.cluster.load.async.to.lds.b128 %{{.*}}, %{{.*}}, 0, 0, 0
+ rocdl.cluster.load.async.to.lds.b8 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.cluster.load.async.to.lds.b32 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.cluster.load.async.to.lds.b64 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ rocdl.cluster.load.async.to.lds.b128 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ llvm.return
+}
+
+
// CHECK-LABEL @rocdl.tensor.load.to.lds
llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
%dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
diff --git a/mlir/test/Target/LLVMIR/rocdl.mlir b/mlir/test/Target/LLVMIR/rocdl.mlir
index dcf80ad4395de..42f80cc2137b9 100644
--- a/mlir/test/Target/LLVMIR/rocdl.mlir
+++ b/mlir/test/Target/LLVMIR/rocdl.mlir
@@ -1097,6 +1097,19 @@ llvm.func @rocdl.global.load.async.to.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3
llvm.return
}
+// CHECK-LABEL: rocdl.cluster.load.async.to.lds
+llvm.func @rocdl.cluster.load.async.to.lds(%src : !llvm.ptr<1>, %dst: !llvm.ptr<3>) {
+ // CHECK: call void @llvm.amdgcn.cluster.load.async.to.lds.b8
+ rocdl.cluster.load.async.to.lds.b8 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ // CHECK: call void @llvm.amdgcn.cluster.load.async.to.lds.b32
+ rocdl.cluster.load.async.to.lds.b32 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ // CHECK: call void @llvm.amdgcn.cluster.load.async.to.lds.b64
+ rocdl.cluster.load.async.to.lds.b64 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ // CHECK: call void @llvm.amdgcn.cluster.load.async.to.lds.b128
+ rocdl.cluster.load.async.to.lds.b128 %src, %dst, 0, 0, 0 : !llvm.ptr<1>, !llvm.ptr<3>
+ llvm.return
+}
+
// CHECK-LABEL: rocdl.tensor.load.to.lds
llvm.func @rocdl.tensor.load.to.lds(%dgroup0 : vector<4xi32>, %dgroup1 : vector<8xi32>,
%dgroup2 : vector<4xi32>, %dgroup3 : vector<4xi32>) {
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