[Mlir-commits] [mlir] [mlir][spirv] Add support for SwitchOp (PR #168713)
Jakub Kuderski
llvmlistbot at llvm.org
Wed Nov 19 07:21:08 PST 2025
================
@@ -242,6 +242,112 @@ def SPIRV_FunctionCallOp : SPIRV_Op<"FunctionCall", [
}];
}
+// -----
+
+def SPIRV_SwitchOp : SPIRV_Op<"Switch",
+ [AttrSizedOperandSegments, InFunctionScope,
+ DeclareOpInterfaceMethods<BranchOpInterface, ["getSuccessorForOperands"]>,
+ Pure, Terminator]> {
+ let summary = [{
+ Multi-way branch to one of the operand label <id>.
+ }];
+
+ let description = [{
+ Selector must have a type of OpTypeInt. Selector is compared for equality to
+ the Target literals.
+
+ Default must be the <id> of a label. If Selector does not equal any of the
+ Target literals, control flow branches to the Default label <id>.
+
+ Target must be alternating scalar integer literals and the <id> of a label.
+ If Selector equals a literal, control flow branches to the following label
+ <id>. It is invalid for any two literal to be equal to each other. If Selector
+ does not equal any literal, control flow branches to the Default label <id>.
+ Each literal is interpreted with the type of Selector: The bit width of
+ Selector’s type is the width of each literal’s type. If this width is not a
+ multiple of 32-bits and the OpTypeInt Signedness is set to 1, the literal values
+ are interpreted as being sign extended.
+
+ If Selector is an OpUndef, behavior is undefined.
+
+ This instruction must be the last instruction in a block.
+
+ #### Example:
+
+ ```mlir
+ spirv.Switch %selector : si32, [
+ default: ^bb1(%a : i32),
+ 0: ^bb1(%b : i32),
+ 1: ^bb3(%c : i32)
+ ]
----------------
kuhar wrote:
Maybe it would be worth expanding this example with contents of the blocks so that it does something?
https://github.com/llvm/llvm-project/pull/168713
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