[Mlir-commits] [mlir] [mlir][amdgpu] lowerings for ScaledExtPacked816 (PR #168123)

[Erick Ochoa Lopez]

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@@ -1613,6 +1613,182 @@ LogicalResult ExtPackedFp8OpLowering::matchAndRewrite(
   return success();
 }
 
+int getScaleSel(int blockSize, int bitWidth, int firstScaleLane,
+                int firstScaleByte) {
+  // When lowering amdgpu.scaled_ext_packed816 to
+  // rocdl.cvt.scale.pk*.f*.f* operations, the
+  // attributes blockSize, sourceType, firstScaleLane and firstScaleByte
+  // are merged into a single attribute scaleSel.
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amd-eochoalo wrote:

https://github.com/llvm/llvm-project/pull/168123/commits/69787933cc44ed01faff7abf38078c0f61917bbd

https://github.com/llvm/llvm-project/pull/168123