[Mlir-commits] [mlir] [mlir][NVVM] Add support for barrier0 operation with predicate (PR #167036)

[Durgadoss R]

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@@ -1007,31 +1025,36 @@ def NVVM_BarrierOp : NVVM_Op<"barrier", [AttrSizedOperandSegments]> {
     [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-bar)
   }];
 
-  let arguments = (ins     
-    Optional<I32>:$barrierId,
-    Optional<I32>:$numberOfThreads);
+  let arguments = (ins Optional<I32>:$barrierId, Optional<I32>:$numberOfThreads,
+      OptionalAttr<BarrierReductionAttr>:$reductionOp,
+      Optional<I32>:$reductionPredicate);
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durga4github wrote:

ah, I think from the Intrinsics layer, we are returning an `i32` for all kinds.

https://github.com/llvm/llvm-project/pull/167036