[Mlir-commits] [mlir] [mlir][NVVM] Add support for barrier0 operation with predicate (PR #167036)

[Durgadoss R]

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@@ -977,6 +977,54 @@ def NVVM_Barrier0Op : NVVM_Op<"barrier0"> {
   }];
 }
 
+// Attrs describing the predicate of barrier0 operation.
+def Barrier0PredPopc : I32EnumAttrCase<"POPC", 0, "popc">;
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durga4github wrote:

ok, I think you are modelling the reduction-operations from here:
https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar

In that case, can we name this attr something like `BarrierReduxKind{Attr -> And/Or/Popc}` ?

https://github.com/llvm/llvm-project/pull/167036