[Mlir-commits] [mlir] [MLIR][XeVM] Update XeVM prefetch ops. (PR #166445)

[Sang Ik Lee]

https://github.com/silee2 created https://github.com/llvm/llvm-project/pull/166445

Prefetch ops need pointer operand marked as MemWrite to avoid getting dead code eliminated. As a reference point, memref.prefetch is handled in a similar way.

>From f39b7263ce9becf2c380de7fdc61ce17268cc906 Mon Sep 17 00:00:00 2001
From: "Lee, Sang Ik" <sang.ik.lee at intel.com>
Date: Tue, 4 Nov 2025 21:10:02 +0000
Subject: [PATCH] [MLIR][XeVM] Update XeVM prefetch ops. Prefetch ops need
 pointer operand marked as MemWrite to avoid getting dead code eliminated. As
 a reference point, memref.prefetch is handled in a similar way.

---
 mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
index 2dd612139fa2d..91e46d68673ed 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/XeVMOps.td
@@ -444,7 +444,8 @@ def XeVM_MemfenceOp
 def XeVM_PrefetchOp
     : XeVM_Op<"prefetch">,
       Arguments<(ins Arg<AnyTypeOf<[LLVM_PointerInAddressSpace<1>,
-                                    LLVM_PointerInAddressSpace<4>]>>:$ptr,
+                                    LLVM_PointerInAddressSpace<4>]>,
+                         "", [MemWrite]>:$ptr,
           OptionalAttr<XeVM_LoadCacheControlAttr>:$cache_control)> {
   let summary = "Prefetch data into a cache subsystem.";
   let description = [{
@@ -463,7 +464,7 @@ def XeVM_PrefetchOp
 
 def XeVM_BlockPrefetch2dOp
     : XeVM_Op<"blockprefetch2d">,
-      Arguments<(ins Arg<LLVM_AnyPointer, "", [MemRead]>:$ptr, I32:$base_width,
+      Arguments<(ins Arg<LLVM_AnyPointer, "", [MemWrite]>:$ptr, I32:$base_width,
           I32:$base_height, I32:$base_pitch, I32:$x, I32:$y,
           I32Attr:$elem_size_in_bits, I32Attr:$tile_width, I32Attr:$tile_height,
           I32Attr:$v_blocks,