[Mlir-commits] [mlir] [mlir][GPU] Fixes subgroup reduce lowering (PR #141825)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Wed May 28 12:44:35 PDT 2025
https://github.com/Muzammiluddin-Syed-ECE updated https://github.com/llvm/llvm-project/pull/141825
>From 7b7e0e5b7e1627a9ffae9f0113ccdbb80687fae8 Mon Sep 17 00:00:00 2001
From: Muzammiluddin Syed <muzasyed at amd.com>
Date: Wed, 28 May 2025 18:53:24 +0000
Subject: [PATCH] [mlir][GPU] Fixes subgroup reduce lowering
Signed-off-by: Muzammiluddin Syed <muzasyed at amd.com>
---
.../GPU/Transforms/SubgroupReduceLowering.cpp | 29 ++++++++++++-------
.../Dialect/GPU/subgroup-reduce-lowering.mlir | 2 +-
2 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp b/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
index 74face4291353..cb9d32bbb1ea7 100644
--- a/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
+++ b/mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
@@ -447,29 +447,36 @@ createSubgroupDPPReduction(PatternRewriter &rewriter, gpu::SubgroupReduceOp op,
if (ci.clusterSize >= 64) {
if (chipset.majorVersion <= 9) {
// Broadcast 31st lane value to rows 2 and 3.
- // Use row mask to avoid polluting rows 0 and 1.
dpp = rewriter.create<amdgpu::DPPOp>(
loc, res.getType(), res, res, amdgpu::DPPPerm::row_bcast_31,
- rewriter.getUnitAttr(), 0xc, allBanks,
- /*bound_ctrl*/ false);
+ rewriter.getUnitAttr(), 0xf, allBanks,
+ /*bound_ctrl*/ true);
+ res = vector::makeArithReduction(
+ rewriter, loc, gpu::convertReductionKind(mode), dpp, res);
+ // Obtain reduction from last rows, the previous rows are polluted.
+ Value lane63 = rewriter.create<arith::ConstantOp>(
+ loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(63));
+ res = rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane63);
} else if (chipset.majorVersion <= 12) {
// Assume reduction across 32 lanes has been done.
// Perform final reduction manually by summing values in lane 0 and
// lane 32.
- Value lane0 = rewriter.create<arith::ConstantOp>(
- loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(0));
- Value lane32 = rewriter.create<arith::ConstantOp>(
- loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(32));
- dpp = rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane32);
- res = rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane0);
+ Value lane31 = rewriter.create<arith::ConstantOp>(
+ loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(31));
+ Value lane63 = rewriter.create<arith::ConstantOp>(
+ loc, rewriter.getI32Type(), rewriter.getI32IntegerAttr(63));
+ lane31 =
+ rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane31);
+ lane63 =
+ rewriter.create<ROCDL::ReadlaneOp>(loc, res.getType(), res, lane63);
+ res = vector::makeArithReduction(
+ rewriter, loc, gpu::convertReductionKind(mode), lane31, lane63);
} else {
return rewriter.notifyMatchFailure(
op, "Subgroup reduce lowering to DPP not currently supported for "
"this device.");
}
- res = vector::makeArithReduction(rewriter, loc,
- gpu::convertReductionKind(mode), res, dpp);
}
assert(res.getType() == input.getType());
return res;
diff --git a/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir b/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
index 098145ade2ae5..87a31ca20eb7b 100644
--- a/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
+++ b/mlir/test/Dialect/GPU/subgroup-reduce-lowering.mlir
@@ -349,7 +349,7 @@ gpu.module @kernels {
// CHECK-GFX10: %[[A4:.+]] = arith.addi %[[A3]], %[[P0]] : i16
// CHECK-GFX10: %[[R0:.+]] = rocdl.readlane %[[A4]], %{{.+}} : (i16, i32) -> i16
// CHECK-GFX10: %[[R1:.+]] = rocdl.readlane %[[A4]], %{{.+}} : (i16, i32) -> i16
- // CHECK-GFX10: %[[A5:.+]] = arith.addi %[[R1]], %[[R0]] : i16
+ // CHECK-GFX10: %[[A5:.+]] = arith.addi %[[R0]], %[[R1]] : i16
// CHECK-GFX10: "test.consume"(%[[A5]]) : (i16) -> ()
%sum0 = gpu.subgroup_reduce add %arg0 : (i16) -> i16
"test.consume"(%sum0) : (i16) -> ()
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