[Mlir-commits] [mlir] [MLIR][NVVM] Update dot.accumulate NVVM Ops (PR #140518)

[Srinivasa Ravi]

================
@@ -3445,25 +3445,28 @@ def NVVM_Tcgen05StOp : NVVM_Op<"tcgen05.st"> {
 }
 
 //===----------------------------------------------------------------------===//
-// NVVM dot.accumulate.4way Op
+// NVVM dot.accumulate Ops
 //===----------------------------------------------------------------------===//
 
-def DotAccumulate4WayS8 : I32EnumAttrCase<"S8", 1, "s8">;
-def DotAccumulate4WayU8 : I32EnumAttrCase<"U8", 0, "u8">;
+def DotAccumulateS8 : I32EnumAttrCase<"S8", 1, "s8">;
+def DotAccumulateU8 : I32EnumAttrCase<"U8", 0, "u8">;
+def DotAccumulateS16 : I32EnumAttrCase<"S16", 2, "s16">;
+def DotAccumulateU16 : I32EnumAttrCase<"U16", 3, "u16">;
----------------
Wolfram70 wrote:

Sorry, I think the names here were misleading. I have renamed it to only `s` and `u` in the latest revision. I did it this way here since this only refers to whether the individual elements will be sign or zero extended (and whether the result by extension is signed or unsigned). Another way to do this would be to use `AnyTypeOf` for the result and the inputs but I'm not sure if that would look clean.

https://github.com/llvm/llvm-project/pull/140518