[Mlir-commits] [mlir] [MLIR][NVVM] Update dot.accumulate NVVM Ops (PR #140518)

[Guray Ozen]

================
@@ -3445,25 +3445,28 @@ def NVVM_Tcgen05StOp : NVVM_Op<"tcgen05.st"> {
 }
 
 //===----------------------------------------------------------------------===//
-// NVVM dot.accumulate.4way Op
+// NVVM dot.accumulate Ops
 //===----------------------------------------------------------------------===//
 
-def DotAccumulate4WayS8 : I32EnumAttrCase<"S8", 1, "s8">;
-def DotAccumulate4WayU8 : I32EnumAttrCase<"U8", 0, "u8">;
+def DotAccumulateS8 : I32EnumAttrCase<"S8", 1, "s8">;
+def DotAccumulateU8 : I32EnumAttrCase<"U8", 0, "u8">;
+def DotAccumulateS16 : I32EnumAttrCase<"S16", 2, "s16">;
+def DotAccumulateU16 : I32EnumAttrCase<"U16", 3, "u16">;
----------------
grypp wrote:

We have added types in the past, at that time, MLIR didn't have all the types that tensor core supports. But now it has. We should cleanup them. 
In the meantime, we can start using MLIR types

https://github.com/llvm/llvm-project/pull/140518