[Mlir-commits] [mlir] [mlir][llvm][x86vector] One-to-one intrinsic op interface (PR #140055)
Tobias Gysi
llvmlistbot at llvm.org
Thu May 15 10:21:14 PDT 2025
================
@@ -382,6 +382,45 @@ LogicalResult LLVM::detail::oneToOneRewrite(
return success();
}
+LogicalResult LLVM::detail::intrinsicRewrite(
+ Operation *op, StringRef intrinsic, ValueRange operands,
+ const LLVMTypeConverter &typeConverter, RewriterBase &rewriter) {
+ auto loc = op->getLoc();
+
+ if (!llvm::all_of(operands, [](Value value) {
+ return LLVM::isCompatibleType(value.getType());
+ }))
+ return failure();
+
+ unsigned numResults = op->getNumResults();
+ Type resType;
+ if (numResults != 0)
+ resType = typeConverter.packOperationResults(op->getResultTypes());
+
+ auto callIntrOp = rewriter.create<LLVM::CallIntrinsicOp>(
+ loc, resType, rewriter.getStringAttr(intrinsic), operands);
+ // Propagate attributes.
+ callIntrOp->setAttrs(op->getAttrDictionary());
+
+ if (numResults <= 1) {
+ // Directly replace the original op.
+ rewriter.replaceOp(op, callIntrOp);
+ return success();
+ }
+
+ // Extract individual results from packed structure and use them as
+ // replacements.
+ SmallVector<Value, 4> results;
+ results.reserve(numResults);
+ Value intrRes = callIntrOp.getResults();
+ for (unsigned i = 0; i < numResults; ++i) {
+ results.push_back(rewriter.create<LLVM::ExtractValueOp>(loc, intrRes, i));
+ }
----------------
gysit wrote:
```suggestion
for (unsigned i = 0; i < numResults; ++i)
results.push_back(rewriter.create<LLVM::ExtractValueOp>(loc, intrRes, i));
```
ultra nit: braces could be dropped here?
https://github.com/llvm/llvm-project/pull/140055
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