[Mlir-commits] [mlir] [MLIR][NVVM] Add `inline_ptx` op (PR #139923)
Guray Ozen
llvmlistbot at llvm.org
Thu May 15 04:28:32 PDT 2025
================
@@ -236,6 +236,76 @@ foreach index = !range(0, 32) in {
def NVVM_EnvReg # index # Op : NVVM_SpecialRegisterOp<"read.ptx.sreg.envreg" # index>;
}
+//===----------------------------------------------------------------------===//
+// Inline PTX op definition
+//===----------------------------------------------------------------------===//
+
+def NVVM_InlinePtxOP : NVVM_Op<"inline_ptx",
+ [DeclareOpInterfaceMethods<BasicPtxBuilderOpInterface>,
+ AttrSizedOperandSegments]>
+{
+ let summary = "Inline PTX Op";
+ let description = [{This op allows using PTX directly within the NVVM
+ dialect, while greatly simplifying llvm.inline_asm generation. It
+ automatically handles register size selection and sets the correct
+ read/write access for each operand. The operation leverages the
----------------
grypp wrote:
Aren't they by default? It's SSA
https://github.com/llvm/llvm-project/pull/139923
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