[Mlir-commits] [mlir] 526ae7f - [mlir][vector] Remove remaining bitwidths from linearization patterns (#138072)

llvmlistbot at llvm.org llvmlistbot at llvm.org
Thu May 1 10:10:30 PDT 2025


Author: James Newling
Date: 2025-05-01T10:10:27-07:00
New Revision: 526ae7ffb5317ebdfab3564c2c5811d1d08259b1

URL: https://github.com/llvm/llvm-project/commit/526ae7ffb5317ebdfab3564c2c5811d1d08259b1
DIFF: https://github.com/llvm/llvm-project/commit/526ae7ffb5317ebdfab3564c2c5811d1d08259b1.diff

LOG: [mlir][vector] Remove remaining bitwidths from linearization patterns (#138072)

In https://github.com/llvm/llvm-project/pull/136581 the bitwidth logic
was supposed to be completely removed from the linearization patterns.
But it was left in a few places. This PR removes the remainders (they
were default valued constructor arguments that were unused).

Added: 
    

Modified: 
    mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp

Removed: 
    


################################################################################
diff  --git a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
index 67e15852dc5ea..b9fdede535112 100644
--- a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
+++ b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp
@@ -21,7 +21,6 @@
 #include "mlir/Transforms/DialectConversion.h"
 #include "llvm/ADT/ArrayRef.h"
 #include <cstdint>
-#include <limits>
 #include <numeric>
 #include <optional>
 
@@ -230,10 +229,8 @@ struct LinearizeVectorExtractStridedSlice final
 struct LinearizeVectorShuffle final
     : public OpConversionPattern<vector::ShuffleOp> {
   using OpConversionPattern::OpConversionPattern;
-  LinearizeVectorShuffle(
-      const TypeConverter &typeConverter, MLIRContext *context,
-      unsigned targetVectBitWidth = std::numeric_limits<unsigned>::max(),
-      PatternBenefit benefit = 1)
+  LinearizeVectorShuffle(const TypeConverter &typeConverter,
+                         MLIRContext *context, PatternBenefit benefit = 1)
       : OpConversionPattern(typeConverter, context, benefit) {}
 
   LogicalResult
@@ -290,10 +287,8 @@ struct LinearizeVectorShuffle final
 struct LinearizeVectorExtract final
     : public OpConversionPattern<vector::ExtractOp> {
   using OpConversionPattern::OpConversionPattern;
-  LinearizeVectorExtract(
-      const TypeConverter &typeConverter, MLIRContext *context,
-      unsigned targetVectBitWidth = std::numeric_limits<unsigned>::max(),
-      PatternBenefit benefit = 1)
+  LinearizeVectorExtract(const TypeConverter &typeConverter,
+                         MLIRContext *context, PatternBenefit benefit = 1)
       : OpConversionPattern(typeConverter, context, benefit) {}
   LogicalResult
   matchAndRewrite(vector::ExtractOp extractOp, OpAdaptor adaptor,
@@ -339,10 +334,8 @@ struct LinearizeVectorExtract final
 struct LinearizeVectorInsert final
     : public OpConversionPattern<vector::InsertOp> {
   using OpConversionPattern::OpConversionPattern;
-  LinearizeVectorInsert(
-      const TypeConverter &typeConverter, MLIRContext *context,
-      unsigned targetVectBitWidth = std::numeric_limits<unsigned>::max(),
-      PatternBenefit benefit = 1)
+  LinearizeVectorInsert(const TypeConverter &typeConverter,
+                        MLIRContext *context, PatternBenefit benefit = 1)
       : OpConversionPattern(typeConverter, context, benefit) {}
   LogicalResult
   matchAndRewrite(vector::InsertOp insertOp, OpAdaptor adaptor,
@@ -408,10 +401,8 @@ struct LinearizeVectorInsert final
 struct LinearizeVectorBitCast final
     : public OpConversionPattern<vector::BitCastOp> {
   using OpConversionPattern::OpConversionPattern;
-  LinearizeVectorBitCast(
-      const TypeConverter &typeConverter, MLIRContext *context,
-      unsigned targetVectBitWidth = std::numeric_limits<unsigned>::max(),
-      PatternBenefit benefit = 1)
+  LinearizeVectorBitCast(const TypeConverter &typeConverter,
+                         MLIRContext *context, PatternBenefit benefit = 1)
       : OpConversionPattern(typeConverter, context, benefit) {}
   LogicalResult
   matchAndRewrite(vector::BitCastOp castOp, OpAdaptor adaptor,


        


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