[Mlir-commits] [mlir] [mlir][nvgpu] update commit group and wait async ops (PR #130482)

[lonely eagle]

linuxlonelyeagle wrote:

> SSA semantics to me implies that these are tracked and honored in the lowering: is it the case though?



> > We also discussed that having an SSA semantic is a design choice.
> 
> SSA semantics to me implies that these are tracked and honored in the lowering: is it the case though?

The tracking was not really done during the lower, but was replaced with zero.So you're tracking content that doesn't make sense.
```
  LogicalResult
  matchAndRewrite(nvgpu::DeviceAsyncCreateGroupOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const override {
    rewriter.create<NVVM::CpAsyncCommitGroupOp>(op.getLoc());
    // Drop the result token.
    Value zero = rewriter.create<LLVM::ConstantOp>(
        op->getLoc(), IntegerType::get(op.getContext(), 32),
        rewriter.getI32IntegerAttr(0));
    rewriter.replaceOp(op, zero);
    rewriter.replaceOpWithNewOp<NVVM::CpAsyncCommitGroupOp>(op);
    return success();
  }
};
```

https://github.com/llvm/llvm-project/pull/130482