[Mlir-commits] [mlir] [mlir][Vector] Infer mask and pass_thru types for maskedload/store (PR #131482)

[Kunwar Grover]

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@@ -1348,55 +1348,58 @@ func.func @store_memref_index_mismatch(%base : memref<?xf32>, %value : vector<16
 
 func.func @maskedload_base_type_mismatch(%base: memref<?xf64>, %mask: vector<16xi1>, %pass: vector<16xf32>) {
   %c0 = arith.constant 0 : index
-  // expected-error at +1 {{'vector.maskedload' op base and result element type should match}}
-  %0 = vector.maskedload %base[%c0], %mask, %pass : memref<?xf64>, vector<16xi1>, vector<16xf32> into vector<16xf32>
+  // expected-error at +1 {{'vector.maskedload' op failed to verify that all of {result, base} have same element type}}
+  %0 = vector.maskedload %base[%c0], %mask, %pass : memref<?xf64>, vector<16xf32>
 }
 
 // -----
 
+  // expected-note at +1 {{prior use here}}
 func.func @maskedload_dim_mask_mismatch(%base: memref<?xf32>, %mask: vector<15xi1>, %pass: vector<16xf32>) {
   %c0 = arith.constant 0 : index
-  // expected-error at +1 {{'vector.maskedload' op expected result shape to match mask shape}}
-  %0 = vector.maskedload %base[%c0], %mask, %pass : memref<?xf32>, vector<15xi1>, vector<16xf32> into vector<16xf32>
+  // expected-error at +1 {{use of value '%mask' expects different type than prior uses: 'vector<16xi1>' vs 'vector<15xi1>'}}
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Groverkss wrote:

Let me see if i can make tablgen emit a better message

https://github.com/llvm/llvm-project/pull/131482