[Mlir-commits] [mlir] [mlir][nvgpu] update commit group and wait async ops (PR #130482)

[Guray Ozen]

grypp wrote:

I think this PR is breaking SSA semantic, this can cause problems right?
Currently we have this ops:
```
%1 = nvgpu.device_async_create_group %0
nvgpu.device_async_wait %1 { numGroups = 1 : i32 }
```
PR makes the ops like the following. There is SSA anymore. 
```
nvgpu.device_async_create_group %0
nvgpu.device_async_wait { numGroups = 1 : i32 }
```

https://github.com/llvm/llvm-project/pull/130482