[Mlir-commits] [mlir] [MLIR][Affine] Fix a crash with invalid cachesize (PR #114722)

Uday Bondhugula llvmlistbot at llvm.org
Sun Mar 9 16:46:07 PDT 2025


bondhugula wrote:

Cache size zero can be considered a valid input and should not signal pass failure for it. Fixed here: https://github.com/llvm/llvm-project/pull/130526

https://github.com/llvm/llvm-project/pull/114722


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