[Mlir-commits] [mlir] [mlir][xegpu] Relax rank restriction of TensorDescType (PR #145916)

[Jianhui Li]

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@@ -213,6 +228,15 @@ gpu.func @simt_load_nd_8(%src: memref<24x32xf32>) {
   gpu.return
 }
 
+// CHECK: func @subgroup_load_nd_9(%[[arg0:.*]]: memref<4x8x16xf16>) {
+gpu.func @subgroup_load_nd_9(%src: memref<4x8x16xf16>) {
+  // CHECK: %[[R0:.*]] = xegpu.create_nd_tdesc %arg0[0, 0, 0] : memref<4x8x16xf16> -> !xegpu.tensor_desc<4x8x16xf16>
+  %1 = xegpu.create_nd_tdesc %src[0, 0, 0] : memref<4x8x16xf16> -> !xegpu.tensor_desc<4x8x16xf16>
+  // CHECK: %[[R1:.*]] = xegpu.load_nd %[[R0]] <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}> : !xegpu.tensor_desc<4x8x16xf16> -> vector<4x8x16xf16>
+  %2 = xegpu.load_nd %1 <{l1_hint = #xegpu.cache_hint<cached>, l2_hint = #xegpu.cache_hint<uncached>}> : !xegpu.tensor_desc<4x8x16xf16> -> vector<4x8x16xf16>
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Jianhui-Li wrote:

The transpose (also  transpose_bit_width) attribute is hard-specific functionality which was provided as internal op semantics on SIMD lowering.  XeGPU user should not use these attributes at the workgroup level, to create a diverged programming model. Instead, user should do load, and then transpose in separate operations. To prevent this, XeGPU should either remove transpose attributes (or mark them SIMD-lowering-only and to be deprecated), or check user input and disallow the transpose attribute attaching to load_nd at workgroup level. 

https://github.com/llvm/llvm-project/pull/145916