[Mlir-commits] [mlir] [mlir][xegpu] add support for structure control flow ops in workgroup to subgroup distribution (PR #142618)
Chao Chen
llvmlistbot at llvm.org
Tue Jun 10 14:10:39 PDT 2025
================
@@ -314,14 +328,64 @@ struct WgToSgPrefetchNdOp : public OpConversionPattern<xegpu::PrefetchNdOp> {
}
};
+// Handles UnrealizedConversionCastOp generated during
+// SCFStructuralTypeConversions (step 1). This op may appear as either a
+// target or source materialization for Vector values, e.g.:
+// 1. unrealized_cast %1 : vector<256xf32> to vector<16xf32>, ...
+// 2. unrealized_cast %1 : vector<16xf32>, ... to vector<256xf32>
+// it could be either 1:N or N:1 cast. In both cases, the pattern
+// simply forwards the inputs to the outputs using 1:1 or 1:N interface.
+// TODO: remove it when context-aware type converter is ready.
+struct UnrealizedConversionCastOpPattern
+ : public OpConversionPattern<mlir::UnrealizedConversionCastOp> {
+ using OpConversionPattern<
+ mlir::UnrealizedConversionCastOp>::OpConversionPattern;
+
+ mlir::LogicalResult
+ matchAndRewrite(mlir::UnrealizedConversionCastOp op, OneToNOpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ SmallVector<Value> inputs = xegpu::flattenValues(adaptor.getInputs());
+
+ auto inputTy = dyn_cast<VectorType>(inputs[0].getType());
+ auto outputTy = dyn_cast<VectorType>(op->getOpResult(0).getType());
+
+ if (!inputTy || !outputTy || !llvm::all_equal(op->getResultTypes()) ||
+ !llvm::all_equal(ValueRange(inputs).getTypes()))
+ return failure();
+
+ // Handles the case where cast %1 : vector<256xf32> to vector<16xf32>, ...
+ // the input values provided by the adaptor should already be distributed,
----------------
chencha3 wrote:
Added an example for the pattern, hope it can help to understand. For arguments and results (N:1 case), they are generated by `SCFStructuralTypeConversions`, for 1:N case, they are generated by patterns of, e.g., create_nd etc.
https://github.com/llvm/llvm-project/pull/142618
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