[Mlir-commits] [mlir] [mlir][gpu][spirv] Remove rotation semantics of gpu.shuffle up/down (PR #139105)

[Hsiangkai Wang]

================
@@ -416,6 +416,30 @@ LogicalResult GPUBarrierConversion::matchAndRewrite(
   return success();
 }
 
+template <typename T>
+Value getDimOp(OpBuilder &builder, MLIRContext *ctx, Location loc,
+               gpu::Dimension dimension) {
+  Type indexType = IndexType::get(ctx);
+  IntegerType i32Type = IntegerType::get(ctx, 32);
+  Value dim = builder.create<T>(loc, indexType, dimension);
+  return builder.create<arith::IndexCastOp>(loc, i32Type, dim);
+}
+
+Value getLaneId(OpBuilder &rewriter, MLIRContext *ctx, Location loc) {
+  Value dimX = getDimOp<gpu::BlockDimOp>(rewriter, ctx, loc, gpu::Dimension::x);
+  Value dimY = getDimOp<gpu::BlockDimOp>(rewriter, ctx, loc, gpu::Dimension::y);
+  Value tidX = getDimOp<gpu::ThreadIdOp>(rewriter, ctx, loc, gpu::Dimension::x);
+  Value tidY = getDimOp<gpu::ThreadIdOp>(rewriter, ctx, loc, gpu::Dimension::y);
+  Value tidZ = getDimOp<gpu::ThreadIdOp>(rewriter, ctx, loc, gpu::Dimension::z);
+  auto i32Type = rewriter.getIntegerType(32);
+  Value tmp1 = rewriter.create<arith::MulIOp>(loc, i32Type, tidZ, dimY);
+  Value tmp2 = rewriter.create<arith::AddIOp>(loc, i32Type, tmp1, tidY);
+  Value tmp3 = rewriter.create<arith::MulIOp>(loc, i32Type, tmp2, dimX);
+  Value laneId = rewriter.create<arith::AddIOp>(loc, i32Type, tmp3, tidX);
----------------
Hsiangkai wrote:

According to SPIR-V specification,

```The set of invocations partitioned in some execution models (e.g. GLCompute, Kernel) as a workgroup. Its size is defined statically by either the WorkgroupSize [built-in](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#BuiltIn)```

We should be able to calculate invocation ID from workgroup sizes and thread IDs under GLCompute, and Kernel execution mode. By the way, there is no conversion pattern to convert gpu::LaneId to SPIR-V. I will add a pattern for it first.


https://github.com/llvm/llvm-project/pull/139105