[Mlir-commits] [mlir] [mlir][AMDGPU] Add scaled floating point conversion ops fp8 (PR #141554)

[llvmlistbot at llvm.org]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
index bbdeb833b..aed9b71c6 100644
--- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -1178,8 +1178,7 @@ struct PackedStochRoundFp8OpLowering final
 
 struct ScaledExtPackedOpLowering final
     : public ConvertOpToLLVMPattern<ScaledExtPackedOp> {
-  ScaledExtPackedOpLowering(const LLVMTypeConverter &converter,
-                               Chipset chipset)
+  ScaledExtPackedOpLowering(const LLVMTypeConverter &converter, Chipset chipset)
       : ConvertOpToLLVMPattern<amdgpu::ScaledExtPackedOp>(converter),
         chipset(chipset) {}
   Chipset chipset;
@@ -1192,18 +1191,16 @@ struct ScaledExtPackedOpLowering final
 struct PackedScaledTruncOpLowering final
     : public ConvertOpToLLVMPattern<PackedScaledTruncOp> {
   PackedScaledTruncOpLowering(const LLVMTypeConverter &converter,
-                                   Chipset chipset)
+                              Chipset chipset)
       : ConvertOpToLLVMPattern<amdgpu::PackedScaledTruncOp>(converter),
         chipset(chipset) {}
   Chipset chipset;
 
   LogicalResult
-  matchAndRewrite(PackedScaledTruncOp op,
-                  PackedScaledTruncOpAdaptor adaptor,
+  matchAndRewrite(PackedScaledTruncOp op, PackedScaledTruncOpAdaptor adaptor,
                   ConversionPatternRewriter &rewriter) const override;
 };
 
-
 } // end namespace
 
 LogicalResult ExtPackedFp8OpLowering::matchAndRewrite(
@@ -1729,7 +1726,7 @@ void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
            AMDGPUDPPLowering, LDSBarrierOpLowering, SchedBarrierOpLowering,
            MFMAOpLowering, ScaledMFMAOpLowering, WMMAOpLowering,
            ExtPackedFp8OpLowering, ScaledExtPackedOpLowering,
-		   PackedScaledTruncOpLowering, PackedTrunc2xFp8OpLowering,
+           PackedScaledTruncOpLowering, PackedTrunc2xFp8OpLowering,
            PackedStochRoundFp8OpLowering, GatherToLDSOpLowering>(converter,
                                                                  chipset);
   patterns.add<AMDGPUSwizzleBitModeLowering>(converter);

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https://github.com/llvm/llvm-project/pull/141554