[Mlir-commits] [mlir] [mlir][spirv] Add OpExtension "SPV_INTEL_tensor_float32_conversion " (PR #151337)

[llvmlistbot at llvm.org]

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@@ -297,13 +300,40 @@ LogicalResult INTELConvertBF16ToFOp::verify() {
 LogicalResult INTELConvertFToBF16Op::verify() {
   auto operandType = getOperand().getType();
   auto resultType = getResult().getType();
-  // ODS checks that vector result type and vector operand type have the same
-  // shape.
-  if (auto vectorType = llvm::dyn_cast<VectorType>(operandType)) {
-    unsigned operandNumElements = vectorType.getNumElements();
-    unsigned resultNumElements =
-        llvm::cast<VectorType>(resultType).getNumElements();
-    if (operandNumElements != resultNumElements) {
+  // ODS checks that vector result type and vector operand type are
+  // non-scalable and have the same shape.
+  auto operandVectorType = dyn_cast<VectorType>(operandType);
+  auto resultVectorType = dyn_cast<VectorType>(resultType);
+  if (operandVectorType && resultVectorType) {
+    if (operandVectorType.isScalable() || resultVectorType.isScalable()) {
+      return emitOpError("scalable vectors are not supported");
+    }
+    if (operandVectorType.getNumElements() !=
+        resultVectorType.getNumElements()) {
+      return emitOpError(
+          "operand and result must have same number of elements");
+    }
+  }
+  return success();
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.INTELRoundFToTF32Op
+//===----------------------------------------------------------------------===//
+
+LogicalResult INTELRoundFToTF32Op::verify() {
+  auto operandType = getOperand().getType();
+  auto resultType = getResult().getType();
+  // ODS checks that vector result type and vector operand type are
+  // non-scalable and have the same shape.
+  auto operandVectorType = dyn_cast<VectorType>(operandType);
+  auto resultVectorType = dyn_cast<VectorType>(resultType);
+  if (operandVectorType && resultVectorType) {
----------------
YixingZhang007 wrote:

Thanks for the suggestion! I have updated the code as follows:
(1) To ensure the operand and result have the same number of elements, we added the `SameOperandsAndResultShape` trait to opRoundFToTF32 in `SPIRVIntelExtOps.td` (https://github.com/llvm/llvm-project/blob/446149f885ef2efadfcdac583c8bbe5d7f1df88a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td#L116)
(2) To restrict the operand and result types to scalar or vector of floats, we specified `SPIRV_ScalarOrVectorOf<SPIRV_Float32>` for both in `SPIRVIntelExtOps.td` (https://github.com/llvm/llvm-project/blob/446149f885ef2efadfcdac583c8bbe5d7f1df88a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td#L149)
(2) To verify that operand and result vectors are non-scalable, we continue to perform this check in the `LogicalResult INTELRoundFToTF32Op::verify()` function in `CastOps.cpp` since I couldn’t find an existing trait suitable for enforcing this (https://github.com/llvm/llvm-project/blob/446149f885ef2efadfcdac583c8bbe5d7f1df88a/mlir/lib/Dialect/SPIRV/IR/CastOps.cpp#L319) 

https://github.com/llvm/llvm-project/pull/151337