[Mlir-commits] [mlir] [mlir][NFC] update `mlir/Dialect` create APIs (29/n) (PR #150642)
Maksim Levental
llvmlistbot at llvm.org
Fri Jul 25 09:03:59 PDT 2025
https://github.com/makslevental created https://github.com/llvm/llvm-project/pull/150642
See https://github.com/llvm/llvm-project/pull/147168 for more info.
>From 86d5e34175b32248914be32dfdf8c66f09c0ec66 Mon Sep 17 00:00:00 2001
From: max <maksim.levental at gmail.com>
Date: Fri, 25 Jul 2025 12:03:33 -0400
Subject: [PATCH] [mlir][NFC] update `mlir/Dialect` create APIs (29/n)
See https://github.com/llvm/llvm-project/pull/147168 for more info.
---
mlir/tools/mlir-tblgen/RewriterGen.cpp | 16 ++--
mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 12 +--
.../tools/tblgen-to-irdl/OpDefinitionsGen.cpp | 92 +++++++++----------
3 files changed, 61 insertions(+), 59 deletions(-)
diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp
index 975a524a53285..67c0aefc7a1d8 100644
--- a/mlir/tools/mlir-tblgen/RewriterGen.cpp
+++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp
@@ -632,7 +632,8 @@ void PatternEmitter::emitOpMatch(DagNode tree, StringRef opName, int depth) {
++opArgIdx;
continue;
}
- if (auto *operand = llvm::dyn_cast_if_present<NamedTypeConstraint *>(opArg)) {
+ if (auto *operand =
+ llvm::dyn_cast_if_present<NamedTypeConstraint *>(opArg)) {
if (argTree.isVariadic()) {
if (!operand->isVariadic()) {
auto error = formatv("variadic DAG construct can't match op {0}'s "
@@ -1695,7 +1696,7 @@ std::string PatternEmitter::handleOpCreation(DagNode tree, int resultIndex,
// Then create the op.
os.scope("", "\n}\n").os
- << formatv("{0} = rewriter.create<{1}>({2}, tblgen_values, {3});",
+ << formatv("{0} = {1}::create(rewriter,{2}, tblgen_values, {3});",
valuePackName, resultOp.getQualCppClassName(), locToUse,
useProperties ? "tblgen_props" : "tblgen_attrs");
return resultValue;
@@ -1714,7 +1715,7 @@ std::string PatternEmitter::handleOpCreation(DagNode tree, int resultIndex,
// aggregate-parameter builders.
createSeparateLocalVarsForOpArgs(tree, childNodeNames);
- os.scope().os << formatv("{0} = rewriter.create<{1}>({2}", valuePackName,
+ os.scope().os << formatv("{0} = {1}::create(rewriter,{2}", valuePackName,
resultOp.getQualCppClassName(), locToUse);
supplyValuesForOpArgs(tree, childNodeNames, depth);
os << "\n );\n}\n";
@@ -1753,7 +1754,7 @@ std::string PatternEmitter::handleOpCreation(DagNode tree, int resultIndex,
resultIndex + i);
}
}
- os << formatv("{0} = rewriter.create<{1}>({2}, tblgen_types, "
+ os << formatv("{0} = {1}::create(rewriter,{2}, tblgen_types, "
"tblgen_values, {3});\n",
valuePackName, resultOp.getQualCppClassName(), locToUse,
useProperties ? "tblgen_props" : "tblgen_attrs");
@@ -1772,8 +1773,8 @@ void PatternEmitter::createSeparateLocalVarsForOpArgs(
int valueIndex = 0; // An index for uniquing local variable names.
for (int argIndex = 0, e = resultOp.getNumArgs(); argIndex < e; ++argIndex) {
- const auto *operand =
- llvm::dyn_cast_if_present<NamedTypeConstraint *>(resultOp.getArg(argIndex));
+ const auto *operand = llvm::dyn_cast_if_present<NamedTypeConstraint *>(
+ resultOp.getArg(argIndex));
// We do not need special handling for attributes or properties.
if (!operand)
continue;
@@ -1828,7 +1829,8 @@ void PatternEmitter::supplyValuesForOpArgs(
Argument opArg = resultOp.getArg(argIndex);
// Handle the case of operand first.
- if (auto *operand = llvm::dyn_cast_if_present<NamedTypeConstraint *>(opArg)) {
+ if (auto *operand =
+ llvm::dyn_cast_if_present<NamedTypeConstraint *>(opArg)) {
if (!operand->name.empty())
os << "/*" << operand->name << "=*/";
os << childNodeNames.lookup(argIndex);
diff --git a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
index 72567057fc5d4..9f72349e20bcd 100644
--- a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
+++ b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
@@ -397,10 +397,9 @@ static void emitAvailabilityQueryForBitEnum(const Record &enumDef,
avail.getMergeInstanceType(), avail.getQueryFnName(),
enumName);
- os << formatv(
- " assert(::llvm::popcount(static_cast<{0}>(value)) <= 1"
- " && \"cannot have more than one bit set\");\n",
- underlyingType);
+ os << formatv(" assert(::llvm::popcount(static_cast<{0}>(value)) <= 1"
+ " && \"cannot have more than one bit set\");\n",
+ underlyingType);
os << " switch (value) {\n";
for (const auto &caseSpecPair : classCasePair.getValue()) {
@@ -933,7 +932,8 @@ static void emitOperandDeserialization(const Operator &op, ArrayRef<SMLoc> loc,
// Process operands/attributes
for (unsigned i = 0, e = op.getNumArgs(); i < e; ++i) {
auto argument = op.getArg(i);
- if (auto *valueArg = llvm::dyn_cast_if_present<NamedTypeConstraint *>(argument)) {
+ if (auto *valueArg =
+ llvm::dyn_cast_if_present<NamedTypeConstraint *>(argument)) {
if (valueArg->isVariableLength()) {
if (i != e - 1) {
PrintFatalError(
@@ -1044,7 +1044,7 @@ static void emitDeserializationFunction(const Record *attrClass,
emitDecorationDeserialization(op, " ", valueID, attributes, os);
os << formatv(" Location loc = createFileLineColLoc(opBuilder);\n");
- os << formatv(" auto {1} = opBuilder.create<{0}>(loc, {2}, {3}, {4}); "
+ os << formatv(" auto {1} = {0}::create(opBuilder,loc, {2}, {3}, {4}); "
"(void){1};\n",
op.getQualCppClassName(), opVar, resultTypes, operands,
attributes);
diff --git a/mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp b/mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
index c2ad09ffaaed5..4343f2d677739 100644
--- a/mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
+++ b/mlir/tools/tblgen-to-irdl/OpDefinitionsGen.cpp
@@ -52,33 +52,33 @@ Value createPredicate(OpBuilder &builder, tblgen::Pred pred) {
}
if (combiner == "PredCombinerAnd") {
auto op =
- builder.create<irdl::AllOfOp>(UnknownLoc::get(ctx), constraints);
+ irdl::AllOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
auto op =
- builder.create<irdl::AnyOfOp>(UnknownLoc::get(ctx), constraints);
+ irdl::AnyOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
}
std::string condition = pred.getCondition();
// Build a CPredOp to match the C constraint built.
- irdl::CPredOp op = builder.create<irdl::CPredOp>(
- UnknownLoc::get(ctx), StringAttr::get(ctx, condition));
+ irdl::CPredOp op = irdl::CPredOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, condition));
return op;
}
Value typeToConstraint(OpBuilder &builder, Type type) {
MLIRContext *ctx = builder.getContext();
auto op =
- builder.create<irdl::IsOp>(UnknownLoc::get(ctx), TypeAttr::get(type));
+ irdl::IsOp::create(builder, UnknownLoc::get(ctx), TypeAttr::get(type));
return op.getOutput();
}
Value baseToConstraint(OpBuilder &builder, StringRef baseClass) {
MLIRContext *ctx = builder.getContext();
- auto op = builder.create<irdl::BaseOp>(UnknownLoc::get(ctx),
- StringAttr::get(ctx, baseClass));
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, baseClass));
return op.getOutput();
}
@@ -179,7 +179,7 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
return createTypeConstraint(builder, predRec.getValueAsDef("baseType"));
if (predRec.getName() == "AnyType") {
- auto op = builder.create<irdl::AnyOp>(UnknownLoc::get(ctx));
+ auto op = irdl::AnyOp::create(builder, UnknownLoc::get(ctx));
return op.getOutput();
}
@@ -190,12 +190,12 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
SmallVector<FlatSymbolRefAttr> nested = {
SymbolRefAttr::get(ctx, combined)};
auto typeSymbol = SymbolRefAttr::get(ctx, dialect, nested);
- auto op = builder.create<irdl::BaseOp>(UnknownLoc::get(ctx), typeSymbol);
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx), typeSymbol);
return op.getOutput();
}
std::string typeName = ("!" + predRec.getValueAsString("typeName")).str();
- auto op = builder.create<irdl::BaseOp>(UnknownLoc::get(ctx),
- StringAttr::get(ctx, typeName));
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, typeName));
return op.getOutput();
}
@@ -205,7 +205,7 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
constraints.push_back(
createTypeConstraint(builder, tblgen::Constraint(child)));
}
- auto op = builder.create<irdl::AnyOfOp>(UnknownLoc::get(ctx), constraints);
+ auto op = irdl::AnyOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
@@ -215,14 +215,14 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
constraints.push_back(
createTypeConstraint(builder, tblgen::Constraint(child)));
}
- auto op = builder.create<irdl::AllOfOp>(UnknownLoc::get(ctx), constraints);
+ auto op = irdl::AllOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
// Integer types
if (predRec.getName() == "AnyInteger") {
- auto op = builder.create<irdl::BaseOp>(
- UnknownLoc::get(ctx), StringAttr::get(ctx, "!builtin.integer"));
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, "!builtin.integer"));
return op.getOutput();
}
@@ -235,7 +235,7 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
IntegerType::get(ctx, width, IntegerType::Signed)),
typeToConstraint(builder,
IntegerType::get(ctx, width, IntegerType::Unsigned))};
- auto op = builder.create<irdl::AnyOfOp>(UnknownLoc::get(ctx), types);
+ auto op = irdl::AnyOfOp::create(builder, UnknownLoc::get(ctx), types);
return op.getOutput();
}
@@ -253,7 +253,7 @@ Value createTypeConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
for (const Record *child : predRec.getValueAsListOfDefs("predicateList")) {
constraints.push_back(createPredicate(builder, tblgen::Pred(child)));
}
- auto op = builder.create<irdl::AllOfOp>(UnknownLoc::get(ctx), constraints);
+ auto op = irdl::AllOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
@@ -279,7 +279,7 @@ Value createAttrConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
constraints.push_back(createPredicate(
builder, tblgen::Pred(child->getValueAsDef("predicate"))));
}
- auto op = builder.create<irdl::AllOfOp>(UnknownLoc::get(ctx), constraints);
+ auto op = irdl::AllOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
@@ -290,12 +290,12 @@ Value createAttrConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
constraints.push_back(
createAttrConstraint(builder, tblgen::Constraint(child)));
}
- auto op = builder.create<irdl::AnyOfOp>(UnknownLoc::get(ctx), constraints);
+ auto op = irdl::AnyOfOp::create(builder, UnknownLoc::get(ctx), constraints);
return op.getOutput();
}
if (predRec.getName() == "AnyAttr") {
- auto op = builder.create<irdl::AnyOp>(UnknownLoc::get(ctx));
+ auto op = irdl::AnyOp::create(builder, UnknownLoc::get(ctx));
return op.getOutput();
}
@@ -317,7 +317,7 @@ Value createAttrConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
if (predRec.getName() == "UnitAttr") {
auto op =
- builder.create<irdl::IsOp>(UnknownLoc::get(ctx), UnitAttr::get(ctx));
+ irdl::IsOp::create(builder, UnknownLoc::get(ctx), UnitAttr::get(ctx));
return op.getOutput();
}
@@ -329,12 +329,12 @@ Value createAttrConstraint(OpBuilder &builder, tblgen::Constraint constraint) {
};
auto typeSymbol = SymbolRefAttr::get(ctx, dialect, nested);
- auto op = builder.create<irdl::BaseOp>(UnknownLoc::get(ctx), typeSymbol);
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx), typeSymbol);
return op.getOutput();
}
std::string typeName = ("#" + predRec.getValueAsString("attrName")).str();
- auto op = builder.create<irdl::BaseOp>(UnknownLoc::get(ctx),
- StringAttr::get(ctx, typeName));
+ auto op = irdl::BaseOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, typeName));
return op.getOutput();
}
@@ -348,15 +348,15 @@ Value createRegionConstraint(OpBuilder &builder, tblgen::Region constraint) {
if (predRec.getName() == "AnyRegion") {
ValueRange entryBlockArgs = {};
auto op =
- builder.create<irdl::RegionOp>(UnknownLoc::get(ctx), entryBlockArgs);
+ irdl::RegionOp::create(builder, UnknownLoc::get(ctx), entryBlockArgs);
return op.getResult();
}
if (predRec.isSubClassOf("SizedRegion")) {
ValueRange entryBlockArgs = {};
auto ty = IntegerType::get(ctx, 32);
- auto op = builder.create<irdl::RegionOp>(
- UnknownLoc::get(ctx), entryBlockArgs,
+ auto op = irdl::RegionOp::create(
+ builder, UnknownLoc::get(ctx), entryBlockArgs,
IntegerAttr::get(ty, predRec.getValueAsInt("blocks")));
return op.getResult();
}
@@ -388,8 +388,8 @@ irdl::OperationOp createIRDLOperation(OpBuilder &builder,
MLIRContext *ctx = builder.getContext();
StringRef opName = getOperatorName(tblgenOp);
- irdl::OperationOp op = builder.create<irdl::OperationOp>(
- UnknownLoc::get(ctx), StringAttr::get(ctx, opName));
+ irdl::OperationOp op = irdl::OperationOp::create(
+ builder, UnknownLoc::get(ctx), StringAttr::get(ctx, opName));
// Add the block in the region.
Block &opBlock = op.getBody().emplaceBlock();
@@ -471,19 +471,19 @@ irdl::OperationOp createIRDLOperation(OpBuilder &builder,
// Create the operands and results operations.
if (!operands.empty())
- consBuilder.create<irdl::OperandsOp>(UnknownLoc::get(ctx), operands,
- ArrayAttr::get(ctx, operandNames),
- operandVariadicity);
+ irdl::OperandsOp::create(consBuilder, UnknownLoc::get(ctx), operands,
+ ArrayAttr::get(ctx, operandNames),
+ operandVariadicity);
if (!results.empty())
- consBuilder.create<irdl::ResultsOp>(UnknownLoc::get(ctx), results,
- ArrayAttr::get(ctx, resultNames),
- resultVariadicity);
+ irdl::ResultsOp::create(consBuilder, UnknownLoc::get(ctx), results,
+ ArrayAttr::get(ctx, resultNames),
+ resultVariadicity);
if (!attributes.empty())
- consBuilder.create<irdl::AttributesOp>(UnknownLoc::get(ctx), attributes,
- ArrayAttr::get(ctx, attrNames));
+ irdl::AttributesOp::create(consBuilder, UnknownLoc::get(ctx), attributes,
+ ArrayAttr::get(ctx, attrNames));
if (!regions.empty())
- consBuilder.create<irdl::RegionsOp>(UnknownLoc::get(ctx), regions,
- ArrayAttr::get(ctx, regionNames));
+ irdl::RegionsOp::create(consBuilder, UnknownLoc::get(ctx), regions,
+ ArrayAttr::get(ctx, regionNames));
return op;
}
@@ -493,8 +493,8 @@ irdl::TypeOp createIRDLType(OpBuilder &builder, tblgen::TypeDef &tblgenType) {
StringRef typeName = getTypeName(tblgenType);
std::string combined = ("!" + typeName).str();
- irdl::TypeOp op = builder.create<irdl::TypeOp>(
- UnknownLoc::get(ctx), StringAttr::get(ctx, combined));
+ irdl::TypeOp op = irdl::TypeOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, combined));
op.getBody().emplaceBlock();
@@ -507,8 +507,8 @@ irdl::AttributeOp createIRDLAttr(OpBuilder &builder,
StringRef attrName = getAttrName(tblgenAttr);
std::string combined = ("#" + attrName).str();
- irdl::AttributeOp op = builder.create<irdl::AttributeOp>(
- UnknownLoc::get(ctx), StringAttr::get(ctx, combined));
+ irdl::AttributeOp op = irdl::AttributeOp::create(
+ builder, UnknownLoc::get(ctx), StringAttr::get(ctx, combined));
op.getBody().emplaceBlock();
@@ -517,8 +517,8 @@ irdl::AttributeOp createIRDLAttr(OpBuilder &builder,
static irdl::DialectOp createIRDLDialect(OpBuilder &builder) {
MLIRContext *ctx = builder.getContext();
- return builder.create<irdl::DialectOp>(UnknownLoc::get(ctx),
- StringAttr::get(ctx, selectedDialect));
+ return irdl::DialectOp::create(builder, UnknownLoc::get(ctx),
+ StringAttr::get(ctx, selectedDialect));
}
static bool emitDialectIRDLDefs(const RecordKeeper &records, raw_ostream &os) {
@@ -529,7 +529,7 @@ static bool emitDialectIRDLDefs(const RecordKeeper &records, raw_ostream &os) {
// Create a module op and set it as the insertion point.
OwningOpRef<ModuleOp> module =
- builder.create<ModuleOp>(UnknownLoc::get(&ctx));
+ ModuleOp::create(builder, UnknownLoc::get(&ctx));
builder = builder.atBlockBegin(module->getBody());
// Create the dialect and insert it.
irdl::DialectOp dialect = createIRDLDialect(builder);
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