[Mlir-commits] [mlir] [MLIR][Wasm] Introduce the WasmSSA MLIR dialect (PR #149233)

[Oleksandr Alex Zinenko]

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@@ -0,0 +1,186 @@
+//===-- WebAssemblySSAInterfaces.td - WebAssemblySSA Interfaces -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines interfaces for the WebAssemblySSA dialect in MLIR.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef WEBASSEMBLYSSA_INTERFACES
+#define WEBASSEMBLYSSA_INTERFACES
+
+include "mlir/IR/OpBase.td"
+include "mlir/IR/BuiltinAttributes.td"
+
+def WasmSSALabelLevelInterface : OpInterface<"WasmSSALabelLevelInterface"> {
+  let description = [{
+    Operation that defines one level of nesting for wasm branching.
+    These operation region can be targeted by branch instructions.
+  }];
+  let methods = [
+    InterfaceMethod<
+      /*desc=*/        "Returns the target block address",
+      /*returnType=*/  "::mlir::Block*",
+      /*methodName=*/  "getLabelTarget",
+      /*args=*/        (ins)
+    >
+  ];
+}
+
+def WasmSSALabelBranchingInterface : OpInterface<"WasmSSALabelBranchingInterface"> {
+  let description = [{
+    Wasm operation that targets a label for a jump.
+  }];
+  let methods = [
+    InterfaceMethod<
+      /*desc=*/        "Returns the number of context to break from",
+      /*returnType=*/  "size_t",
+      /*methodName=*/  "getExitLevel",
+      /*args=*/        (ins)
+    >,
----------------
ftynse wrote:

IIUC, the `wasmssa.if` is itself a terminator operation that has successor blocks. So the control flows from `block_return` to the parent `wasmssa.if` and then to its successor, forwarding the data along. This sounds fine wrt LangRef. Though we may have to double-check that control flow interfaces handle this correctly, i.e., one op can implement both `RegionBranchOpInterface` and `RegionBranchTerminatorOpInterface` without breaking anything.

What I don't see in the example is the nested-if situation. Is there a possibility to exit from multiple nesting levels immediately?

https://github.com/llvm/llvm-project/pull/149233