[Mlir-commits] [mlir] [MLIR][AArch64] Change some tests to ensure SVE vector length is the same throughout the function (PR #147506)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Tue Jul 8 04:11:38 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: Momchil Velikov (momchil-velikov)
<details>
<summary>Changes</summary>
This change only applies to functions the can be reasonably expected to use SVE registers.
Modifying vector length in the middle of a function might cause incorrect stack deallocation if there are callee-saved SVE registers or incorrect access to SVE stack slots.
---
Full diff: https://github.com/llvm/llvm-project/pull/147506.diff
4 Files Affected:
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir (+6-5)
- (modified) mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir (+5)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir (+5-5)
- (modified) mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir (-4)
``````````diff
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
index bca94d4a64416..399896905eb66 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-scalable-inner-tile.mlir
@@ -39,6 +39,12 @@ func.func @main() {
[ 7, 14, 21, 28, 35, 42, 49, 56, 63, 70, 77, 84, 91, 98, 105, 112]
]> : tensor<7x16xi32>
+
+ // Set vscale to 2 (vector width = 256). This will have identical effect to:
+ // * qemu-aarch64 -cpu max,sve-max-vq=2 (...)
+ %c256 = arith.constant 256 : i32
+ func.call @setArmVLBits(%c256) : (i32) -> ()
+
func.call @pack(%A) : (tensor<7x16xi32>) -> ()
return
@@ -48,11 +54,6 @@ func.func private @pack(%A: tensor<7x16xi32>) {
%c1 = arith.constant 1 : index
%pad_val = arith.constant 123 : i32
- // Set vscale to 2 (vector width = 256). This will have identical effect to:
- // * qemu-aarch64 -cpu max,sve-max-vq=2 (...)
- %c256 = arith.constant 256 : i32
- func.call @setArmVLBits(%c256) : (i32) -> ()
-
// Scalable tile size
%vs = vector.vscale
%c8 = arith.constant 8 : index
diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir
index 128e5f7412fb2..4c49dc6f66529 100644
--- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir
+++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/pack-unpack-scalable-inner-tile.mlir
@@ -21,7 +21,12 @@ func.func @main() {
// (If your platform supports it, you can play with other values as well)
%c256 = arith.constant 256 : i32
func.call @setArmVLBits(%c256) : (i32) -> ()
+ func.call @test_pack_unpack_scalable_inner_tile() : () -> ()
+ return
+}
+
+func.func @test_pack_unpack_scalable_inner_tile() {
// Dynamic/scalable tile size (vscale x 4)
%c4 = arith.constant 4 : index
%vs = vector.vscale
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir
index 36fdb60d3e7bf..a162cc88b1332 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/transfer-read-scalable-non-trailing.mlir
@@ -15,9 +15,7 @@
// Test the transfer_read with vector type with a non-trailing scalable
// dimension as transformed by the pattern LegalizeTransferRead.
-func.func @transfer_read_scalable_non_trailing(%vs : i32, %M : memref<?x8xi8>) {
- func.call @setArmVLBits(%vs) : (i32) -> ()
-
+func.func @transfer_read_scalable_non_trailing(%M : memref<?x8xi8>) {
// Read an LLVM-illegal vector
%c0 = arith.constant 0 : index
%c0_i8 = arith.constant 0 : i8
@@ -56,14 +54,16 @@ func.func @main() {
// CHECK:( 31, 32, 33, 34, 35, 36, 37, 38, 41, 42, 43, 44, 45, 46, 47, 48 )
vector.print str "Result(VL128):\n"
%c128 = arith.constant 128 : i32
- func.call @transfer_read_scalable_non_trailing(%c128, %MM) : (i32, memref<?x8xi8>) -> ()
+ func.call @setArmVLBits(%c128) : (i32) -> ()
+ func.call @transfer_read_scalable_non_trailing(%MM) : (memref<?x8xi8>) -> ()
// CHECK-LABEL: Result(VL256):
// CHECK: ( 11, 12, 13, 14, 15, 16, 17, 18, 21, 22, 23, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38, 41, 42, 43, 44, 45, 46, 47, 48 )
// CHECK: ( 51, 52, 53, 54, 55, 56, 57, 58, 61, 62, 63, 64, 65, 66, 67, 68, 71, 72, 73, 74, 75, 76, 77, 78, 81, 82, 83, 84, 85, 86, 87, 88 )
vector.print str "Result(VL256):\n"
%c256 = arith.constant 256 : i32
- func.call @transfer_read_scalable_non_trailing(%c256, %MM) : (i32, memref<?x8xi8>) -> ()
+ func.call @setArmVLBits(%c256) : (i32) -> ()
+ func.call @transfer_read_scalable_non_trailing(%MM) : (memref<?x8xi8>) -> ()
return
}
diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir
index 5f6e8e4c30892..be368f5f50666 100644
--- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir
+++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/vector-contract-i8mm.mlir
@@ -131,10 +131,6 @@ func.func @test_smmla() {
%acc_mem = func.call @prepareAccTestData(%acc_cst) : (vector<4x4xi32>) -> memref<4x?xi32>
%acc = vector.transfer_read %acc_mem[%c0, %c0], %c0_i32 {in_bounds = [true, true]} : memref<4x?xi32>, vector<4x[4]xi32>
- // FIXME: Workaround for a crash, see https://github.com/llvm/llvm-project/issues/143670
- %acc_cast = memref.cast %acc_mem : memref<4x?xi32> to memref<*xi32>
- call @printMemrefI32(%acc_cast) : (memref<*xi32>) -> ()
-
// LHS test data
%lhs_cst = arith.constant dense<[[-35, -27, -36, -31, 23, -34, -8, -33],
[-20, 17, -32, -47, 37, 22, -7, -21],
``````````
</details>
https://github.com/llvm/llvm-project/pull/147506
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