[Mlir-commits] [mlir] [mlir][x86vector] AVX512-BF16 Dot op (PR #124800)

[Diego Caballero]

dcaballe wrote:

I haven't thought too deeply about this but I believe the current structure of the `x86Vector` dialect may not scale well as we add more operations. Here are a couple of guiding principles to consider: 

1. For targets that do not support certain instructions, such as AVX512, we might want to avoid loading those operations into the dialect registry. Among other benefits, this would prevent us from generating illegal instructions. We could achieve this by creating independent dialects (e.g., `x86.avx512`, `x86.avx2`, `x86.sseXY`). 

2. We should also consider extending the previous point to AVX-512 sub-ISAs with the same goals: do not load unsupported operations or generate illegal instructions. 

I wonder if we could find a way to conditionally register operations within the same dialect. This approach would help us implement the second point without having to create an independent dialect for each sub-ISA. However, if this conditional registration is not feasible, creating separate dialects for each sub-ISA doesn’t sound terrible to me, esp. if we plan to add a significant number of operations. 

It would be great to take some actions on this regard before things get out of control...

https://github.com/llvm/llvm-project/pull/124800