[Mlir-commits] [mlir] [MLIR][XeGPU] Allow some nd ops to have argument shapes mismatch for … (PR #120566)

[Chao Chen]

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@@ -73,6 +73,32 @@ static bool isWriteHintOrNone(const CachePolicyAttr &attr) {
          kind == CachePolicy::WRITE_BACK || kind == CachePolicy::WRITE_THROUGH;
 }
 
+// Validations for nd instruction arguments is successful if any of these are
+// true:
+// - tensor descriptor and the output vector shapes exactly match.
+// - tensor descriptor has a sg_map attribute and the distributed vector shape
+//   matches the tensor descriptor shape when scaled using sg_map factors on
+//   each dimension.
+static bool isArgShapesValid(ArrayRef<int64_t> descShape,
+                             ArrayRef<int64_t> valShape, SGMapAttr sgMap) {
+  if (descShape == valShape)
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chencha3 wrote:

NVM, it seems a dumb question. It seems to me that, there are currently 3 stages: 1) pure SIMD code, `sgMap == null`, and `descShape == valShape`. 2). a valid sgMap is attached to guide the lowering, but the code is not rewritten yet, so we have `descShape == valShape` and `sgMap != null`, but sgMap is not effective yet. 3). code is rewritten, so `descShape != valShape`, and `sgMap != null`, and sgMap is now effective. 

https://github.com/llvm/llvm-project/pull/120566