[Mlir-commits] [mlir] [MLIR][NVVM] Declare InferIntRangeInterface for RangeableRegisterOp (PR #122263)

[Guray Ozen]

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@@ -0,0 +1,28 @@
+// RUN: mlir-opt -int-range-optimizations -canonicalize %s | FileCheck %s
+gpu.module @module{
+    gpu.func @kernel_1() kernel {
+        %tidx = nvvm.read.ptx.sreg.tid.x range <i32, 0, 32> : i32
+        %tidy = nvvm.read.ptx.sreg.tid.y range <i32, 0, 128> : i32
+        %tidz = nvvm.read.ptx.sreg.tid.z range <i32, 0, 4> : i32
+        %c64 = arith.constant 64 : i32
+        
+        %1 = arith.cmpi sgt, %tidx, %c64 : i32
+        scf.if %1 {
+            gpu.printf "threadidx"
+        }
+        %2 = arith.cmpi sgt, %tidy, %c64 : i32
+        scf.if %2 {
+            gpu.printf "threadidy"
+        }
+        %3 = arith.cmpi sgt, %tidz, %c64 : i32
+        scf.if %3 {
+            gpu.printf "threadidz"
+        }
+        gpu.return
+    }
+}
+
----------------
grypp wrote:

>Without the "int-range-opts" in the cmd-line, will all three "gpu.printf"s be present? Yes! 

The PR enables inferring ranges of OPs. So if you pass only `mlir-opt -int-range-optimizations` will result this code below:
```
$ mlir-opt nvvm-test-range.mlir -int-range-optimizations 

module {
  gpu.module @module {
    gpu.func @kernel_1() kernel {
      %false = arith.constant false
      %c64_i32 = arith.constant 64 : i32
      %0 = nvvm.read.ptx.sreg.tid.y range <i32, 0, 128> : i32
      scf.if %false {
        gpu.printf "threadidx"
      }
      %1 = arith.cmpi sgt, %0, %c64_i32 : i32
      scf.if %1 {
        gpu.printf "threadidy"
      }
      scf.if %false {
        gpu.printf "threadidz"
      }
      gpu.return
    }
  }
}
```

https://github.com/llvm/llvm-project/pull/122263