[Mlir-commits] [mlir] [mlir] Rewrites for I2 to I8 signed and unsigned extension (PR #121298)

[Andrzej Warzyński]

================
@@ -1172,70 +1176,144 @@ Value BitCastRewriter::genericRewriteStep(
   return runningResult;
 }
 
-/// Rewrite the i4 -> i8 signed extension into a sequence of shuffles and
-/// bitwise ops that take advantage of high-level information to avoid leaving
-/// LLVM to scramble with peephole optimizations.
-static Value rewriteI4ToI8SignedExt(PatternRewriter &rewriter, Location loc,
-                                    Value srcValue) {
-  VectorType srcVecType = cast<VectorType>(srcValue.getType());
-  assert(srcVecType.getElementType().isSignlessInteger(4) &&
-         "Expected i4 type");
+/// takes a aligned subByte vector as Input and bitcasts it to a vector of i8.
----------------
banach-space wrote:

Please make sure to start sentences with capital case. Also:
```suggestion
/// Takes an aligned sub-byte vector as Input and bitcasts it to a vector of i8.
```

In fact, why not:
```
Bitcasts the aligned `subByteVec` vector to a vector of i8.
```

Also:
1. Please define to what "aligned" means (referring to `alignedConversionPrecondition` is fine).
2. `scrValue` -> `subByteVec`?

https://github.com/llvm/llvm-project/pull/121298