[Mlir-commits] [mlir] [MLIR] Fix printing of switch case for negative value (PR #129266)
Robert Konicar
llvmlistbot at llvm.org
Fri Feb 28 08:28:21 PST 2025
https://github.com/Jezurko created https://github.com/llvm/llvm-project/pull/129266
This patch fixes the printer for the `llvm.switch` operation with negative values in a case.
The previous behaviour printed the value as an unsigned integer, as the `getLimitedValue()` returns unsigned value. This caused the roundtrip to fail (assertion in `APInt`), as the printed unsigned integer could not be parsed into the same amount of bits in a signed integer.
I don't see a good reason for keeping any restriction on the printed value, as LLVMIR `switch` afaik does not have a limit on the bitwidth of the values and `APInt` handles printing just fine.
>From 7f3420eeb5be5b0230c8d35c20d2c3bcddb958c0 Mon Sep 17 00:00:00 2001
From: Robert Konicar <xkonicar at fi.muni.cz>
Date: Fri, 28 Feb 2025 17:17:35 +0100
Subject: [PATCH] [MLIR] Fix printing of switch case for negative value
This patch fixes the printer for the llvm.switch operation with negative values in a case.
---
mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 2 +-
mlir/test/Dialect/LLVMIR/roundtrip.mlir | 6 ++++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index ccf8f72b2b230..fb9236fcc640d 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -634,7 +634,7 @@ static void printSwitchOpCases(OpAsmPrinter &p, SwitchOp op, Type flagType,
llvm::zip(caseValues, caseDestinations),
[&](auto i) {
p << " ";
- p << std::get<0>(i).getLimitedValue();
+ p << std::get<0>(i);
p << ": ";
p.printSuccessorAndUseList(std::get<1>(i), caseOperands[index++]);
},
diff --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
index 09a0cd57e2675..e0a17308af828 100644
--- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir
+++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir
@@ -144,12 +144,14 @@ func.func @ops(%arg0: i32, %arg1: f32,
// CHECK: llvm.switch %0 : i32, ^[[BB3]] [
// CHECK-NEXT: 1: ^[[BB4:.*]],
// CHECK-NEXT: 2: ^[[BB5:.*]],
- // CHECK-NEXT: 3: ^[[BB6:.*]]
+ // CHECK-NEXT: 3: ^[[BB6:.*]],
+ // CHECK-NEXT: -3: ^[[BB6:.*]]
// CHECK-NEXT: ]
llvm.switch %0 : i32, ^bb3 [
1: ^bb4,
2: ^bb5,
- 3: ^bb6
+ 3: ^bb6,
+ -3: ^bb6
]
// CHECK: ^[[BB3]]
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