[Mlir-commits] [mlir] [mlir][AMDGPU] Enable emulating vector buffer_atomic_fadd for bf16 on gfx942 (PR #129029)

[Daniel Hernandez-Juarez]

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@@ -189,6 +189,14 @@ void mlir::amdgpu::populateAmdgpuEmulateAtomicsPatterns(
     } else {
       target.addIllegalOp<RawBufferAtomicFmaxOp>();
     }
+    // gfx950 has bf16 atomics
+    if (chipset < Chipset(9, 5, 0)) {
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dhernandez0 wrote:

This type of check is done in this cpp already (for Chipset(9, 0, 8)). I agree this is not the best way to handle this, but that seems like a refactor that could be done in a future PR?

https://github.com/llvm/llvm-project/pull/129029