[Mlir-commits] [mlir] [mlir][AMDGPU] Enable emulating vector buffer_atomic_fadd for bf16 on gfx942 (PR #129029)

[Krzysztof Drewniak]

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@@ -189,6 +189,14 @@ void mlir::amdgpu::populateAmdgpuEmulateAtomicsPatterns(
     } else {
       target.addIllegalOp<RawBufferAtomicFmaxOp>();
     }
+    // gfx950 has bf16 atomics
+    if (chipset < Chipset(9, 5, 0)) {
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krzysz00 wrote:

This pass is for handling the MLIR ops that correspond to buffer intrinsics. `ptr addrspace(7)` will go through backend atomic handling.

(This pass is useful for code that doesn't/can't (ex. Triton setting cache modifiers) use buffer fat pointers).

Also ... we don't have access to subtarget features

https://github.com/llvm/llvm-project/pull/129029