[Mlir-commits] [mlir] [mlir][xegpu] Improve XeGPU op verification logic for SIMT flavor and update tests. (PR #127920)

[Artem Kroviakov]

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@@ -239,6 +244,7 @@ LogicalResult TensorDescType::verify(
     llvm::ArrayRef<int64_t> shape, mlir::Type elementType,
     mlir::Attribute encoding, mlir::Attribute sg_map) {
   size_t rank = shape.size();
+  unsigned packingFactor = 32 / elementType.getIntOrFloatBitWidth();
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akroviakov wrote:

It may be worth to make `32` a named variable just to clarify its meaning right away, this could also spare a comment below.

> This is because each work item access data in 32 bit granularity

https://github.com/llvm/llvm-project/pull/127920