[Mlir-commits] [mlir] [mlir][xegpu] Improve XeGPU op verification logic for SIMT flavor and update tests. (PR #127920)

[Charitha Saumya]

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@@ -276,14 +280,13 @@ LogicalResult TensorDescType::verify(
     if (scatterAttr) {
       // Validate subgroup mapping rules for scattered tensors.
       // A work-item's slice of the tensor with shape [sg_size] or
-      // [sg_size, chunk_size] will be [1] or [1, chunks_size] respectively,
-      // the mapping should reflect that.
+      // [sg_size, chunk_size] will be [1] or [1, 32/element_ty_bit_width]
+      // respectively, the mapping should reflect that.
       if (wiData[0] != 1)
         return emitError()
                << "cannot map over non-contiguous scattered row elements";
 
-      unsigned chunkSize = scatterAttr.getChunkSize().getInt();
-      if (wiData[1] != chunkSize)
+      if (wiData[1] != (32 / elementType.getIntOrFloatBitWidth()))
----------------
charithaintc wrote:

> Hmm okay I see. So, 32-bit is the only supported size? I thought the given examples were DPAS-centric but I could push `wi_data` to larger sizes for elementwise operations etc.

ah. I see your point. `wi_data` would not capture this. it only describes how many data elements are owned by a work item before round robin assignment is applied. so it carries the information about "packing".

https://github.com/llvm/llvm-project/pull/127920