[Mlir-commits] [mlir] [mlir][xegpu] Improve XeGPU op verification logic for SIMT flavor and update tests. (PR #127920)

Adam Siemieniuk llvmlistbot at llvm.org
Fri Feb 21 02:38:39 PST 2025


================
@@ -276,14 +280,13 @@ LogicalResult TensorDescType::verify(
     if (scatterAttr) {
       // Validate subgroup mapping rules for scattered tensors.
       // A work-item's slice of the tensor with shape [sg_size] or
-      // [sg_size, chunk_size] will be [1] or [1, chunks_size] respectively,
-      // the mapping should reflect that.
+      // [sg_size, chunk_size] will be [1] or [1, 32/element_ty_bit_width]
+      // respectively, the mapping should reflect that.
       if (wiData[0] != 1)
         return emitError()
                << "cannot map over non-contiguous scattered row elements";
 
-      unsigned chunkSize = scatterAttr.getChunkSize().getInt();
-      if (wiData[1] != chunkSize)
+      if (wiData[1] != (32 / elementType.getIntOrFloatBitWidth()))
----------------
adam-smnk wrote:

> > From where is this rule derived? Does this try to capture the 512 bytes limit for all work items?
> 
> yes. each WI gets 32 bits. I have added a comment for clarification.

Sorry, I still don't follow this check.

First of all which do you try to address - bits or bytes?
Then from the documentation:
>  the total size accessed by all work items are restricted to 512 bytes. And for low-precision data, e.g., fp16 and int8, the total accessed size per work item should also be 32-bit aligned if it is not accessing 1 element. Therefore, for fp16, for example, a valid chunk size could be 2, 4, 8, 16, 32, 64, and for int8, a valid chunk size could be 4, 8, 16, 32, 64.

What I gathered from earlier discussions and (trying to follow) distribution rules, `chunk_size` (memory property) should be equal to the number of elements accessed by work item (distribution property). The only other 32-bit restriction I can see relate to VNNI packing.

So, I'm not sure what I'm missing. Shouldn't we verify both `chunk_size` vs `wi_data` and 32-bit alignment? 

https://github.com/llvm/llvm-project/pull/127920


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