[Mlir-commits] [mlir] [mlir][vector] Fix masked load/store emulation for rank-0 memrefs (PR #173325)

[Prathamesh Tagore]

meshtag wrote:

Thanks for the feedback. 

> The other solution would be making sure that rank-0 memrefs do not expect indices and the logic that currently fails has a special case for this. This solution wouldn't require injecting new Ops. Why not select this approach instead?

Yes, this makes sense. I think I didn't recollect that `memref.load/store` would be fine with no index for the rank 0 memref case. Updated the code with this logic. Thanks.

https://github.com/llvm/llvm-project/pull/173325