[Mlir-commits] [mlir] [mlir][x86vector] Shuffle FMAs (PR #172823)

[Arun Thangamani]

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@@ -0,0 +1,309 @@
+// RUN: mlir-opt %s -transform-interpreter -cse -split-input-file | FileCheck %s
+
+!vec = vector<8xf32>
+!memrefA = memref<1x1x1xbf16>
+!memrefB = memref<1x8x2xbf16>
+
+func.func @shuffle_fma_lhs_even_index(
+  %arg0: !memrefA, %arg1: !memrefA, %arg2: !memrefB, %arg3: !memrefA,
+  %arg4: !memrefA, %arg5: !memrefB, %arg6: !vec) -> !vec
+{
+  %0 = x86vector.avx.bcst_to_f32.packed %arg0 : !memrefA -> !vec
+  %1 = x86vector.avx.cvt.packed.odd.indexed_to_f32 %arg2 : !memrefB -> !vec
+  %2 = vector.fma %0, %1, %arg6 : !vec
+  %3 = x86vector.avx.bcst_to_f32.packed %arg1 : !memrefA -> !vec
+  %4 = x86vector.avx.cvt.packed.even.indexed_to_f32 %arg2 : !memrefB -> !vec
+  %5 = vector.fma %3, %4, %2 : !vec
+  %6 = x86vector.avx.bcst_to_f32.packed %arg3 : !memrefA -> !vec
+  %7 = x86vector.avx.cvt.packed.odd.indexed_to_f32 %arg5 : !memrefB -> !vec
+  %8 = vector.fma %6, %7, %arg6 : !vec
+  %9 = x86vector.avx.bcst_to_f32.packed %arg4 : !memrefA -> !vec
+  %10 = x86vector.avx.cvt.packed.even.indexed_to_f32 %arg5 : !memrefB -> !vec
+  %11 = vector.fma %9, %10, %8 : !vec
+  %12 = vector.fma %5, %11, %arg6 : !vec
+  return %12 : !vec
+}
+
+// CHECK-LABEL: @shuffle_fma_lhs_even_index
+// CHECK: x86vector.avx.bcst_to_f32.packed
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arun-thmn wrote:

True. Updated the `+ve` test-cases with `SSA` values. That should help.

https://github.com/llvm/llvm-project/pull/172823