[Mlir-commits] [mlir] [mlir][amdgpu] Lower make_gather_dma_descriptor. (PR #172083)
llvmlistbot at llvm.org
llvmlistbot at llvm.org
Fri Dec 12 13:13:46 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Erick Ochoa Lopez (amd-eochoalo)
<details>
<summary>Changes</summary>
* Makes `MakeDescriptorOp` a template for `make_dma_descriptor` and `make_gather_dma_descriptor`.
* Makes verification and folder for `make_dma_descriptor` a template.
* Adds custom verification and folder for `make_dma_gather_descriptor` based on tempalte.
* Adds `make_gather_dma_descriptor` op.
* Lowers `make_gather_dma_descriptor` to ROCDL.
---
Patch is 46.28 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172083.diff
6 Files Affected:
- (modified) mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td (+62-28)
- (modified) mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp (+186-53)
- (modified) mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp (+60-26)
- (modified) mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir (+142)
- (modified) mlir/test/Dialect/AMDGPU/amdgpu-make-dma-descriptor-fold.mlir (+21-1)
- (modified) mlir/test/Dialect/AMDGPU/invalid.mlir (+10)
``````````diff
diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
index a0b8682965b20..701414b0e89fd 100644
--- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
+++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
@@ -1360,10 +1360,11 @@ def AMDGPU_MakeDmaBaseOp : AMDGPU_DmaBaseOp<"make_dma_base", AMDGPU_TDMBaseType>
}];
}
-def AMDGPU_MakeDmaDescriptorOp :
- AMDGPU_Op<"make_dma_descriptor", [Pure, AttrSizedOperandSegments]>,
- Arguments<(ins
- AMDGPU_TDMBaseType: $base,
+class AMDGPU_MakeDescriptorOp<string mnemonic> :
+ AMDGPU_Op<mnemonic, [Pure, AttrSizedOperandSegments]>,
+ Results<(outs AMDGPU_TDMDescriptorType: $desc)> {
+
+ dag baseArgs = (ins
Variadic<Index>: $global_dynamic_sizes,
DenseI64ArrayAttr: $global_static_sizes,
Variadic<Index>: $global_dynamic_strides,
@@ -1378,9 +1379,63 @@ def AMDGPU_MakeDmaDescriptorOp :
Variadic<Index>: $atomic_barrier_indices,
Optional<Index>: $global_increment,
Optional<I32>: $lds_increment,
- Optional<Index>: $iteration_count)>,
- Results<(outs AMDGPU_TDMDescriptorType: $desc)> {
+ Optional<Index>: $iteration_count);
+
+ let extraClassDeclaration = [{
+ int64_t getRank() {
+ return getGlobalStaticSizes().size();
+ }
+
+ unsigned getElementTypeWidth() {
+ return getBase().getType().getElementType().getIntOrFloatBitWidth();
+ }
+
+ SmallVector<OpFoldResult> getMixedGlobalSizes() {
+ return getMixedValues(getGlobalStaticSizes(), getGlobalDynamicSizes(), getContext());
+ }
+
+ SmallVector<OpFoldResult> getMixedGlobalStrides() {
+ return getMixedValues(getGlobalStaticStrides(), getGlobalDynamicStrides(), getContext());
+ }
+
+ SmallVector<OpFoldResult> getMixedSharedSizes() {
+ return getMixedValues(getSharedStaticSizes(), getSharedDynamicSizes(), getContext());
+ }
+
+ constexpr bool isGather() {
+ return isa<TDMGatherBaseType>(getBase().getType());
+ }
+ }];
+}
+
+def AMDGPU_MakeGatherDmaDescriptorOp : AMDGPU_MakeDescriptorOp<"make_gather_dma_descriptor"> {
+ dag args = (ins AMDGPU_TDMGatherBaseType: $base,
+ Optional<AnyTypeOf<[VectorOfLengthAndType<[1, 2, 3, 4, 5, 6, 7, 8], [I16, I32]>,
+ VectorOfLengthAndType<[9, 10, 11, 12, 13, 14, 15, 16], [I16]>]>>: $indices);
+ let arguments = !con(args, baseArgs);
+ let summary = "Make all descriptor groups needed by TensorLoadToLDS/TensorStoreFromLDS.";
+
+ let assemblyFormat = [{
+ $base ( `[` $indices^ `]` )?
+ `globalSize` custom<DynamicIndexList>($global_dynamic_sizes, $global_static_sizes)
+ `globalStride` custom<DynamicIndexList>($global_dynamic_strides, $global_static_strides)
+ `sharedSize` custom<DynamicIndexList>($shared_dynamic_sizes, $shared_static_sizes)
+ ( `padShared` `(` $pad_amount^ `every` $pad_interval `)` )?
+ ( `workgroupMask` $workgroup_mask^ ( `earlyTimeout` $early_timeout^)?)?
+ ( `atomicBarrier` `(` $atomic_barrier_address^ `[` $atomic_barrier_indices `]`
+ `:` type($atomic_barrier_address) `)`)?
+ ( `iterate` $global_increment^ `,` $lds_increment `,` $iteration_count )?
+ attr-dict `:` qualified(type($base)) ( `,` type($indices)^ )? `->` type(results)
+ }];
+
+ let hasVerifier = 1;
+ let hasFolder = 1;
+}
+
+def AMDGPU_MakeDmaDescriptorOp : AMDGPU_MakeDescriptorOp<"make_dma_descriptor"> {
+ dag args = (ins AMDGPU_TDMBaseType: $base);
+ let arguments = !con(args, baseArgs);
let summary = "Make all descriptor groups needed by TensorLoadToLDS/TensorStoreFromLDS.";
let description = [{
Make all descriptor groups needed by tensor memory operations.
@@ -1437,30 +1492,9 @@ def AMDGPU_MakeDmaDescriptorOp :
attr-dict `:` qualified(type($base)) `->` type(results)
}];
- let extraClassDeclaration = [{
- int64_t getRank() {
- return getGlobalStaticSizes().size();
- }
-
- unsigned getElementTypeWidth() {
- return getBase().getType().getElementType().getIntOrFloatBitWidth();
- }
-
- SmallVector<OpFoldResult> getMixedGlobalSizes() {
- return getMixedValues(getGlobalStaticSizes(), getGlobalDynamicSizes(), getContext());
- }
-
- SmallVector<OpFoldResult> getMixedGlobalStrides() {
- return getMixedValues(getGlobalStaticStrides(), getGlobalDynamicStrides(), getContext());
- }
-
- SmallVector<OpFoldResult> getMixedSharedSizes() {
- return getMixedValues(getSharedStaticSizes(), getSharedDynamicSizes(), getContext());
- }
- }];
-
let hasVerifier = 1;
let hasFolder = 1;
+
}
#endif // AMDGPU
diff --git a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
index 455e59c4a272a..b776d8e2d9ec1 100644
--- a/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
+++ b/mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
@@ -2382,19 +2382,18 @@ struct AMDGPUMakeDmaBaseLowering : public ConvertOpToLLVMPattern<BaseOp> {
}
};
-struct AMDGPUMakeDmaDescriptorLowering
- : public ConvertOpToLLVMPattern<MakeDmaDescriptorOp> {
- using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
+template <typename DescriptorOp>
+struct AMDGPULowerDescriptor : public ConvertOpToLLVMPattern<DescriptorOp> {
+ using ConvertOpToLLVMPattern<DescriptorOp>::ConvertOpToLLVMPattern;
+ using OpAdaptor = typename ConvertOpToLLVMPattern<DescriptorOp>::OpAdaptor;
- AMDGPUMakeDmaDescriptorLowering(const LLVMTypeConverter &converter,
- Chipset chipset)
- : ConvertOpToLLVMPattern<MakeDmaDescriptorOp>(converter),
- chipset(chipset) {}
+ AMDGPULowerDescriptor(const LLVMTypeConverter &converter, Chipset chipset)
+ : ConvertOpToLLVMPattern<DescriptorOp>(converter), chipset(chipset) {}
Chipset chipset;
Value getDGroup0(OpAdaptor adaptor) const { return adaptor.getBase(); }
- Value setWorkgroupMask(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setWorkgroupMask(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0) const {
Value mask = op.getWorkgroupMask();
@@ -2408,7 +2407,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, extendedMask, 0);
}
- Value setDataSize(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setDataSize(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
unsigned elementTypeWidthInBits = op.getElementTypeWidth();
@@ -2419,7 +2418,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, size, 16);
}
- Value setAtomicBarrier(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setAtomicBarrier(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!adaptor.getAtomicBarrierAddress())
@@ -2428,16 +2427,18 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, consts[1], 18);
}
- Value setIterateEnable(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setIterateEnable(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!adaptor.getGlobalIncrement())
return sgpr0;
+ // Value is ignored when in gather mode.
+ // TODO: emit error earlier?
return setValueAtOffset(rewriter, loc, sgpr0, consts[1], 19);
}
- Value setPadEnable(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setPadEnable(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!op.getPadAmount())
@@ -2446,7 +2447,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, consts[1], 20);
}
- Value setEarlyTimeout(MakeDmaDescriptorOp op, OpAdaptor adaptorm,
+ Value setEarlyTimeout(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!op.getWorkgroupMask())
@@ -2455,7 +2456,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, consts[1], 21);
}
- Value setPadInterval(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setPadInterval(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!op.getPadAmount())
@@ -2476,7 +2477,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, padInterval, 22);
}
- Value setPadAmount(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setPadAmount(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
if (!op.getPadAmount())
@@ -2494,7 +2495,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, padAmount, 25);
}
- Value setAtomicBarrierAddress(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setAtomicBarrierAddress(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter,
Location loc, Value sgpr1,
ArrayRef<Value> consts) const {
@@ -2505,9 +2506,9 @@ struct AMDGPUMakeDmaDescriptorLowering
auto barrierAddressTy =
cast<MemRefType>(op.getAtomicBarrierAddress().getType());
ValueRange atomicBarrierIndices = adaptor.getAtomicBarrierIndices();
- atomicBarrierAddress =
- getStridedElementPtr(rewriter, loc, barrierAddressTy,
- atomicBarrierAddress, atomicBarrierIndices);
+ atomicBarrierAddress = ConvertToLLVMPattern::getStridedElementPtr(
+ rewriter, loc, barrierAddressTy, atomicBarrierAddress,
+ atomicBarrierIndices);
IntegerType i32 = rewriter.getI32Type();
// pre-condition: atomicBarrierAddress is aligned to 8 bytes which implies
// that the 3 LSBs are zero.
@@ -2524,8 +2525,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr1, atomicBarrierAddress, 32);
}
- std::pair<Value, Value> setTensorDimX(MakeDmaDescriptorOp op,
- OpAdaptor adaptor,
+ std::pair<Value, Value> setTensorDimX(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter,
Location loc, Value sgpr1, Value sgpr2,
ArrayRef<Value> consts, uint64_t dimX,
@@ -2561,8 +2561,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return {sgpr1, sgpr2};
}
- std::pair<Value, Value> setTensorDim0(MakeDmaDescriptorOp op,
- OpAdaptor adaptor,
+ std::pair<Value, Value> setTensorDim0(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter,
Location loc, Value sgpr1, Value sgpr2,
ArrayRef<Value> consts) const {
@@ -2570,8 +2569,7 @@ struct AMDGPUMakeDmaDescriptorLowering
48);
}
- std::pair<Value, Value> setTensorDim1(MakeDmaDescriptorOp op,
- OpAdaptor adaptor,
+ std::pair<Value, Value> setTensorDim1(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter,
Location loc, Value sgpr2, Value sgpr3,
ArrayRef<Value> consts) const {
@@ -2579,7 +2577,7 @@ struct AMDGPUMakeDmaDescriptorLowering
80);
}
- Value setTileDimX(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setTileDimX(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr, ArrayRef<Value> consts, size_t dimX,
int64_t offset) const {
@@ -2611,26 +2609,55 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr, tileDimX, offset);
}
- Value setTileDim0(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setTileDim0(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr3, ArrayRef<Value> consts) const {
return setTileDimX(op, adaptor, rewriter, loc, sgpr3, consts, 0, 112);
}
- Value setTileDim1(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setTileDim1(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr4, ArrayRef<Value> consts) const {
return setTileDimX(op, adaptor, rewriter, loc, sgpr4, consts, 1, 128);
}
- Value setTileDim2(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setValidIndices(DescriptorOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter, Location loc,
+ Value sgpr4, ArrayRef<Value> consts) const {
+ MakeGatherDmaDescriptorOp descriptorOp =
+ cast<MakeGatherDmaDescriptorOp>(op);
+ if (!descriptorOp.getIndices())
+ return sgpr4;
+
+ auto type = cast<VectorType>(descriptorOp.getIndices().getType());
+ ArrayRef<int64_t> shape = type.getShape();
+ assert(shape.size() == 1 && "expected shape to be of rank 1.");
+ unsigned length = shape.back();
+ assert(0 < length && length <= 16 && "expected length to be at most 16.");
+ Value value = createI32Constant(rewriter, loc, length);
+ return setValueAtOffset(rewriter, loc, sgpr4, value, 128);
+ }
+
+ Value setTileDim1OrValidIndices(DescriptorOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter,
+ Location loc, Value sgpr4,
+ ArrayRef<Value> consts) const {
+ if (op.isGather())
+ return setValidIndices(op, adaptor, rewriter, loc, sgpr4, consts);
+ return setTileDim1(op, adaptor, rewriter, loc, sgpr4, consts);
+ }
+
+ Value setTileDim2(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr4, ArrayRef<Value> consts) const {
+ // Value is ignored when in gather mode.
+ if (op.isGather())
+ return sgpr4;
return setTileDimX(op, adaptor, rewriter, loc, sgpr4, consts, 2, 144);
}
std::pair<Value, Value>
- setTensorDimXStride(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ setTensorDimXStride(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgprY, Value sgprZ, ArrayRef<Value> consts,
size_t dimX, int64_t offset) const {
@@ -2676,7 +2703,7 @@ struct AMDGPUMakeDmaDescriptorLowering
}
std::pair<Value, Value>
- setTensorDim0Stride(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ setTensorDim0Stride(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr5, Value sgpr6, ArrayRef<Value> consts) const {
return setTensorDimXStride(op, adaptor, rewriter, loc, sgpr5, sgpr6, consts,
@@ -2684,14 +2711,17 @@ struct AMDGPUMakeDmaDescriptorLowering
}
std::pair<Value, Value>
- setTensorDim1Stride(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ setTensorDim1Stride(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr5, Value sgpr6, ArrayRef<Value> consts) const {
+ // Value is ignored when in gather mode.
+ if (op.isGather())
+ return {sgpr5, sgpr6};
return setTensorDimXStride(op, adaptor, rewriter, loc, sgpr5, sgpr6, consts,
1, 208);
}
- Value getDGroup1(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value getDGroup1(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
ArrayRef<Value> consts) const {
Value sgprs[8];
@@ -2716,7 +2746,8 @@ struct AMDGPUMakeDmaDescriptorLowering
setTensorDim1(op, adaptor, rewriter, loc, sgprs[2], sgprs[3], consts);
sgprs[3] = setTileDim0(op, adaptor, rewriter, loc, sgprs[3], consts);
- sgprs[4] = setTileDim1(op, adaptor, rewriter, loc, sgprs[4], consts);
+ sgprs[4] =
+ setTileDim1OrValidIndices(op, adaptor, rewriter, loc, sgprs[4], consts);
sgprs[4] = setTileDim2(op, adaptor, rewriter, loc, sgprs[4], consts);
std::tie(sgprs[5], sgprs[6]) = setTensorDim0Stride(
op, adaptor, rewriter, loc, sgprs[5], sgprs[6], consts);
@@ -2736,7 +2767,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return dgroup1;
}
- Value setTensorDimX(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setTensorDimX(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts, int64_t dimX,
int64_t offset) const {
@@ -2761,7 +2792,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, sgpr0, tensorDimX, offset);
}
- Value setTensorDim2(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setTensorDim2(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr0, ArrayRef<Value> consts) const {
return setTensorDimX(op, adaptor, rewriter, loc, sgpr0, consts, 2, 0);
@@ -2776,7 +2807,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return setValueAtOffset(rewriter, loc, accumulator, value, shift);
}
- Value setLDSAddrIncrement(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setLDSAddrIncrement(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr1, ArrayRef<Value> consts,
int64_t offset) const {
@@ -2785,7 +2816,7 @@ struct AMDGPUMakeDmaDescriptorLowering
}
std::pair<Value, Value>
- setGlobalAddrIncrement(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ setGlobalAddrIncrement(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter, Location loc,
Value sgpr2, Value sgpr3, ArrayRef<Value> consts,
int64_t offset) const {
@@ -2803,8 +2834,7 @@ struct AMDGPUMakeDmaDescriptorLowering
return {sgpr2, sgpr3};
}
- Value setTensorDim3OrLDSAddrIncrement(MakeDmaDescriptorOp op,
- OpAdaptor adaptor,
+ Value setTensorDim3OrLDSAddrIncrement(DescriptorOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter,
Location loc, Value sgpr1,
ArrayRef<Value> consts) const {
@@ -2819,9 +2849,8 @@ struct AMDGPUMakeDmaDescriptorLowering
}
std::pair<Value, Value> setTensorDim2StrideOrGlobalAddrIncrement(
- MakeDmaDescriptorOp op, OpAdaptor adaptor,
- ConversionPatternRewriter &rewriter, Location loc, Value sgpr2,
- Value sgpr3, ArrayRef<Value> consts) const {
+ DescriptorOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter,
+ Location loc, Value sgpr2, Value sgpr3, ArrayRef<Value> consts) const {
Value globalIncrement = op.getGlobalIncrement();
constexpr int32_t dim = 2;
constexpr int32_t offset = 64;
@@ -2832,7 +2861,7 @@ struct AMDGPUMakeDmaDescriptorLowering
consts, offset);
}
- Value setIterateCount(MakeDmaDescriptorOp op, OpAdaptor adaptor,
+ Value setIterateCount(Descr...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/172083
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