[Mlir-commits] [mlir] [mlir][amdgpu] Add tensor load store operations (PR #170918)
Erick Ochoa Lopez
llvmlistbot at llvm.org
Tue Dec 9 06:50:09 PST 2025
================
@@ -2710,6 +2705,37 @@ struct AMDGPUMakeDmaDescriptorLowering
}
};
+template <typename SourceOp, typename TargetOp>
+struct AMDGPUTensorLoadStoreOpLowering
+ : public ConvertOpToLLVMPattern<SourceOp> {
+ using ConvertOpToLLVMPattern<SourceOp>::ConvertOpToLLVMPattern;
+ using Adaptor = typename ConvertOpToLLVMPattern<SourceOp>::OneToNOpAdaptor;
+ AMDGPUTensorLoadStoreOpLowering(const LLVMTypeConverter &converter,
+ Chipset chipset)
+ : ConvertOpToLLVMPattern<SourceOp>(converter), chipset(chipset) {}
+ Chipset chipset;
+
+ LogicalResult
+ matchAndRewrite(SourceOp op, Adaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ if (chipset < kGfx1250)
+ return op->emitOpError("is only supported on gfx1250");
+
+ ValueRange desc = adaptor.getDesc();
+ uint32_t temporalHint = static_cast<uint32_t>(op.getTemporalHint());
+ bool nonVolatile = !static_cast<bool>(op.getIsVolatile());
+ uint32_t cacheScope = static_cast<uint32_t>(op.getCacheScope());
----------------
amd-eochoalo wrote:
https://github.com/llvm/llvm-project/pull/170918/commits/bcc301ce1ab0ecfc4816659401dc1efd7f05e5cb I remove one static cast. The return types of the methods are enums. (The operation's attributes being queried are defined as I32IntAttribute).
https://github.com/llvm/llvm-project/pull/170918
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