[Mlir-commits] [mlir] [mlir][amdgpu] Add tensor load store operations (PR #170918)

[Jakub Kuderski]

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@@ -2728,6 +2754,28 @@ struct ConvertAMDGPUToROCDLPass
       Type i32 = IntegerType::get(type.getContext(), 32);
       return converter.convertType(VectorType::get(4, i32));
     });
+    converter.addConversion(
+        [&](TDMDescriptorType type,
+            SmallVectorImpl<Type> &result) -> std::optional<LogicalResult> {
+          Type i32 = IntegerType::get(type.getContext(), 32);
+          Type v4i32 = converter.convertType(VectorType::get(4, i32));
+          Type v8i32 = converter.convertType(VectorType::get(8, i32));
+          result.push_back(v4i32);
+          result.push_back(v8i32);
+          result.push_back(v4i32);
+          result.push_back(v4i32);
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kuhar wrote:

nit/optional: we have `llvm::append_values(range, v0, v1, v2, v3, ..)` for repeated push backs

https://github.com/llvm/llvm-project/pull/170918