[Mlir-commits] [mlir] [mlir][AMDGPU] Add PermlaneOp (PR #154345)
Tim Gymnich
llvmlistbot at llvm.org
Thu Aug 21 03:12:10 PDT 2025
================
@@ -656,6 +656,60 @@ def AMDGPU_SwizzleBitModeOp : AMDGPU_Op<"swizzle_bitmode",
}];
}
+def AMDGPU_PermlanePerm : I32EnumAttr<"PermlanePerm",
+ "The possible permutations for a permlane operation",
+ [
+ I32EnumAttrCase<"swap_16", 0>,
+ I32EnumAttrCase<"swap_32", 1>,
+ ]> {
+ let genSpecializedAttr = 0;
+ let cppNamespace = "::mlir::amdgpu";
+}
+
+def AMDGPU_PermlanePermAttr : EnumAttr<AMDGPU_Dialect, AMDGPU_PermlanePerm,
+ "permlane_perm">;
+
+def AMDGPU_PermlaneOp : AMDGPU_Op<"permlane", [Pure, AllTypesMatch<["result", "src"]>]>,
+Arguments<(ins AnyIntegerOrFloatOr1DVector:$src,
+ AMDGPU_PermlanePermAttr:$kind,
+ DefaultValuedAttr<BoolAttr, "false">:$fetch_inactive,
+ DefaultValuedAttr<BoolAttr, "false">:$bound_ctrl)> {
+ let summary = "AMDGPU permlane op";
+ let description = [{
+ High-level wrapper on `rocdl.permlane.*` variants.
+
+ Supports arbitrary int/float/vector types, which will be repacked to i32 and
+ one or more `rocdl.permlane.*` ops during lowering.
+ The following lane permutations are supported:
+ - Swap the data between odd and even rows of 16 lanes (`swap_16`)
+ - Swap the data between the first 32 lanes and the last 32 lanes (`swap_32`)
+
+ Format example:
+ ```
+ %0 = amdgpu.permlane %src swap_16 : f16
+ %1 = amdgpu.permlane %src swap_32 { fetch_inactive = true, bound_ctrl = true } : f16
+ ```
+
+ Operands:
+ * `$src`: Vector register to permute across lanes
+ * `$kind`: The kind of permutation operation.
+ * `$fetch_inactive`: Optional. Used to dertermine behavior of invalid lanes (disabled thread or out-of-range).
----------------
tgymnich wrote:
The documentation for these flags was taken from the ISA manual. I guess the distinction between invalid and out-of-bounds does not really apply to permlane. So I replaced invalid and out-of-bounds with disabled lane.
https://github.com/llvm/llvm-project/pull/154345
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