[Mlir-commits] [mlir] [MLIR][NVVM] Improve inline_ptx, add readwrite support (PR #154358)

[Guray Ozen]

grypp wrote:

> This looks really cool, I don't have concerns scanning through it, hopefully someone can double check all the logic as well!

The only nontrivial part is the register numbering. For example, in the snippet below the mapping should be:
`rw0=0, rw1=1, w0=2, w1=3, r0=4, r1=5`.

```
 setp.ge.s32 p,   {$r0},  {$r1};
 selp.s32    {$rw0}, {$r0}, {$r1}, p;
 selp.s32    {$rw1}, {$r0}, {$r1}, p;
 selp.s32    {$w0},  {$r0}, {$r1}, p;
 selp.s32    {$w1},  {$r0}, {$r1}, p;
```


https://github.com/llvm/llvm-project/pull/154358